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blackfin and the blackfi n logo are registered tradem arks of analog devices, inc. blackfin dual core embedded processor adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel: 781.329.4700 ?2013 analog devices, inc. all rights reserved. technical support www.analog.com features dual-core symmetric high-performance blackfin processor, up to 500 mhz per core each core contains two 16-bit macs, two 40-bit alus, and a 40-bit barrel shifter risc-like register and instruction model for ease of ? programming and comp iler-friendly support advanced debug, trace, an d performance monitoring pipelined vision processor prov ides hardware to process sig- nal and image algorithms used for pre- and co-processing of video frames in adas or other video processing applications accepts a range of supply voltages for i/o operation. see operating conditions on page 52 off-chip voltage regulator interface 349-ball bga package (19 mm 19 mm), rohs compliant memory each core contains 148k bytes of l1 sram memory (proces- sor core-accessible) with multi-parity bit protection up to 256k bytes of l2 sram memory with ecc protection dynamic memory controller prov ides 16-bit interface to a single bank of ddr2 or lpddr dram devices static memory controller with asynchronous memory inter- face that supports 8-bit and 16-bit memories 4 memory-to-memory dma streams, 2 of which feature crc protection flexible booting options from flash, sd emmc and spi mem- ories and from spi, link port and uart hosts memory management unit provides memory protection figure 1. processor block diagram system control blocks peripherals hardware functions external bus interfaces lpddr ddr2 crc pipelined vision processor pixel compositor dma system 3 ppi 4 link port 2 emac with 2 ieee 1588 emmc/rsi 3 sport 2 spi 2 uart 1 can 8 timer 2 pwm 1 counter 2 twi usb 2.0 hs otg l2 memory 256k byte ecc- protected sram 32k byte rom 112 gp i/o flash sram emulator test & control pll & power management fault management event control dual watchdog core 1 148k byte parity bit protected l1 sram instruction/data b 1 acm 16 16 dynamic memory controller static memory controller video subsystem core 0 148k byte parity bit protected l1 sram instruction/data b
rev. 0 | page 2 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 blackfin processor core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 instruction set description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 processor infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 memory architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 video subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 processor safety features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 additional processor peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 power and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 system debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 additional information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 related signal chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 adsp-bf60x detailed signal descriptions . . . . . . . . . . . . . . . . . . . 19 349-ball csp_bga signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 23 gp i/o multiplexing for 349-ball csp_bga . . . . . . . . . . . . . . . . . 33 adsp-bf60x designer quick reference . . . . . . . . . . . . . . . . . . . . . . 37 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 processor absolute maximum ratings . . . . . . . . . . . . . . . . . . 58 esd sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 processor package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 output drive currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 environmental conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 adsp-bf60x 349-ball csp_bga ball assignments . . . . . . 103 349-ball csp_bga ball assignme nt (numerical by ball number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 349-ball csp_bga ball assignme nt (alphabetical by pin name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 349-ball csp_bga ball configuration . . . . . . . . . . . . . . . . . . . 107 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 surface-mount design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 automotive products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 revision history 6/13revision 0: initial version.
rev. 0 | page 3 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 general description the adsp-bf60x processors ar e members of the blackfin ? family of products, incorporat ing the analog devices/intel micro signal architecture (msa). blackfin processors combine a dual-mac state-of-the-art signal processing engine, the advantages of a clean, orthog onal risc-like microprocessor instruction set, and single-instruction, multiple-data (simd) multimedia capabili ties into a single instruction-set architecture. the processors offer performance up to 500 mhz, as well as low static power consumpt ion. produced with a low-power and low- voltage design methodology, th ey provide world-class power management and performance. by integrating a rich set of indu stry-leading system peripherals and memory (shown in table 1 ), blackfin processors are the platform of choice for next-gener ation applications that require risc-like programmability, multimedia support, and leading- edge signal processing in one in tegrated package. these applica- tions span a wide array of markets, from au tomotive systems to embedded industrial, instrumentation and power/motor con- trol applications. blackfin processor core as shown in figure 1 , the processor integrates two blackfin pro- cessor cores. each core, shown in figure 2, contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit alus, four video alus, and a 40-bit shifter. the computation units process 8-, 16-, or 32-bit data from the register file. the compute register file contai ns eight 32-bit registers. when performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. all operands for compute operations come from the multiported register file and instruction constant fields. each mac can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. signed and unsigned formats, rounding, and saturation ? are supported. the alus perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. in addition, many special instructions are included to acce lerate various signal processing tasks. these include bit operations such as field extract and pop- ulation count, modulo 2 32 multiply, divide primitives, saturation and rounding, and sign/exponent detection. the set of video instructions include byte alignment and packing operations, ? 16-bit and 8-bit adds with cli pping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (saa) operations. also provided are the compare/select and vector search instructions. for certain instructions, two 16-bit alu operations can be per- formed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a co mpute register). if the second alu is used, quad 16-bit operations are possible. table 1. processor comparison processor feature adsp-bf606 adsp-bf607 ADSP-BF608 adsp-bf609 up/down/rotary counters 1 timer/counters with pwm 8 3-phase pwm units (4-pair) 2 sports 3 spis 2 usb otg 1 parallel peripheral interface 3 removable storage interface 1 can 1 twi 2 uart 2 adc control module (acm) 1 link ports 4 ethernet mac (ieee 1588) 2 pixel compositor (pixc) no 1 1 pipelined vision processor ? (pvp) video resolution 1 no vga hd maximum pvp line buffer size n/a 640 1280 gpios 112 memory (bytes, per core) l1 instruction sram 64k l1 instruction sram/cache 16k l1 data sram 32k l1 data sram/cache 32k l1 scratchpad 4k l2 data sram 128k 256k l2 boot rom 32k maximum speed grade (mhz) 2 400 500 maximum sysclk (mhz) 250 package options 349-ball csp_bga 1 vga is 640 480 pixels per frame. hd is 1280 960 pixels per frame. 2 maximum speed grade is not available with every possible sysclk selection. table 1. processor comparison (continued) processor feature adsp-bf606 adsp-bf607 ADSP-BF608 adsp-bf609
rev. 0 | page 4 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 the 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions. the program sequencer controls the flow of instruction execu- tion, including instruction alignment and decoding. for program flow control, the sequ encer supports pc relative and indirect conditional jumps (with static branch prediction), and subroutine calls. hardware supports zero-overhead looping. the architecture is fully interlocked, meaning that the program- mer need not manage the pipeline when executing instructions with data dependencies. the address arithmetic unit prov ides two addresses for simulta- neous dual fetches from memory. it contains a multiported register file consisti ng of four sets of 32-bit index, modify, length, and base registers (for circular buffering), and eight additional 32-bit pointer regist ers (for c-style indexed stack manipulation). blackfin processors support a modified harvard architecture in combination with a hierarchical memory structure. level 1 (l1) memories are those that typically operate at the full processor speed with little or no latency. at the l1 level, the instruction memory holds instructions only. the data memory holds data, and a dedicated scratchpad data memory stores stack and local variable information. in addition, multiple l1 memory blocks are provided, offering a configurable mix of sram an d cache. the memory manage- ment unit (mmu) provides memory protection for individual tasks that may be oper ating on the core and can protect system registers from unintended access. the architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. user mode has restricted access to certain syst em resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources. instruction set description the blackfin processor instruction set has been optimized so that 16-bit opcodes represent the most frequently used instruc- tions, resulting in excellent co mpiled code density. complex dsp instructions are encoded into 32-bit opcodes, representing fully featured multifunction inst ructions. blackfin processors support a limited multi-issue ca pability, where a 32-bit instruc- tion can be issued in parallel with two 16-bit instructions, allowing the programmer to use ma ny of the core resources in a single instruction cycle. the blackfin processor family a ssembly language instruction set employs an algebraic syntax designed for ease of coding and readability. the instructions have been specifically tuned to pro- vide a flexible, densely encoded instruction set that compiles to figure 2. blackfin processor core sequencer align decode loop buffer 16 16 8 88 8 40 40 a0 a1 barrel shifter data arithmetic unit control unit r7.h r6.h r5.h r4.h r3.h r2.h r1.h r0.h r7.l r6.l r5.l r4.l r3.l r2.l r1.l r0.l astat 40 40 32 32 32 32 32 32 32 ld0 ld1 sd dag0 dag1 address arithmetic unit i3 i2 i1 i0 l3 l2 l1 l0 b3 b2 b1 b0 m3 m2 m1 m0 sp fp p5 p4 p3 p2 p1 p0 da1 da0 32 32 32 preg rab 32 to memory
rev. 0 | page 5 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 a very small final memory size. th e instruction set also provides fully featured multifunction instructions that allow the pro- grammer to use many of the proce ssor core resources in a single instruction. coupled with many features more often seen on microcontrollers, this instruction set is very efficient when com- piling c and c++ source code. in addition, the architecture supports both user (algorithm/app lication code) and supervisor (o/s kernel, device drivers, debuggers, isrs) modes of opera- tion, allowing multiple levels of access to core ? processor resources. the assembly language, which takes advantage of the proces- sors unique architecture, offe rs the following advantages: ? seamlessly integrated dsp/mcu features are optimized for both 8-bit and 16-bit operations. ? a multi-issue load/store modified-harvard architecture, which supports two 16-bit mac or four 8-bit alu + two load/store + two pointer updates per cycle. ? all registers, i/o, and memory are mapped into a unified 4g byte memory space, prov iding a simplified program- ming model. ? control of all asynchronous and synchronous events to the processor is handled by two subsystems: the core event controller (cec) and the syst em event controller (sec). ? microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and ex traction; integer operations on 8-, 16-, and 32-bit data-typ es; and separate user and supervisor stack pointers. ? code density enhancements, wh ich include intermixing of 16-bit and 32-bit instructions (n o mode switching, no code segregation). frequently used instructions are encoded ? in 16 bits. processor infrastructure the following sections provide information on the primary infrastructure components of the adsp-bf609 processor. dma controllers the processor uses direct memo ry access (dma) to transfer data within memory spaces or between a memory space and a peripheral. the processor can spec ify data transfer operations and return to normal processing while the fully integrated dma controller carries out the data transfers independent of proces- sor activity. dma transfers can occur between memory and a peripheral or between one memory and another memory. each memory-to- memory dma stream uses two ch annels, where one channel is the source channel, and the second is the destination channel. all dmas can transport data to and from all on-chip and off- chip memories. programs can use two types of dma transfers, descriptor-based or register-bas ed. register-based dma allows the processor to directly progra m dma control registers to ini- tiate a dma transfer. on comple tion, the control registers may be automatically updated with their original setup values for continuous transfer. descriptor -based dma transfers require a set of parameters stored with in memory to initiate a dma sequence. descriptor-based dm a transfers allow multiple dma sequences to be chained together and a dma channel can be programmed to automatically set up and start another dma transfer after the curr ent sequence completes. the dma controller supports th e following dma operations. ? a single linear buffer th at stops on completion. ? a linear buffer with negative, positive or zero stride length. ? a circular, auto-refreshing buffer that interrupts when each buffer becomes full. ? a similar buffer that interrupts on fractional buffers (for example, 1/2, 1/4). ? 1d dma C uses a set of identical ping-pong buffers defined by a linked ring of two-word descriptor sets, each contain- ing a link pointer and an address. ? 1d dma C uses a linked list of 4 word descriptor sets con- taining a link pointer, an address, a length, and a configuration. ? 2d dma C uses an array of on e-word descriptor sets, spec- ifying only the base dma address. ? 2d dma C uses a linked list of multi-word descriptor sets, specifying everything. crc protection the two crc protection modules a llow system software to peri- odically calculate the signature of code and/or data in memory, the content of memory-mapped registers, or communication message objects. dedicated hard ware circuitry compares the signature with pre calculated values and triggers appropriate fault events. for example, every 100 ms the system software might initiate the signature calculation of the entire memory contents and compare these contents with expected, pre calculated values. if a mismatch occurs, a fault condit ion can be generated (via the processor core or the trigger routing unit). the crc is a hardware module based on a crc32 engine that computes the crc value of the 32-bit data words presented to it. data is provided by the source channel of the memory-to- memory dma (in memory scan mode) and is optionally for- warded to the destination chan nel (memory transfer mode). the main features of the crc peripheral are: ?memory scan mode ?memory transfer mode ?data verify mode ? data fill mode ? user-programmable crc32 polynomial ? bit/byte mirroring option (endianness) ? fault/error interrupt mechanisms ? 1d and 2d fill block to initialize array with constants. ? 32-bit crc signature of a block of a memory or mmr block.
rev. 0 | page 6 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 event handling the processor provides event handling that supports both nest- ing and prioritization. nesting allows multiple event service routines to be active simultaneously. prioritization ensures that servicing of a higher-priority event takes precedence over ser- vicing of a lower-priority event. the processor provides support for five different types of events: ? emulation C an emulation ev ent causes the processor to enter emulation mode, allowing command and control of the processor via the jtag interface. ? reset C this event resets the processor. ? nonmaskable interrupt (nmi ) C the nmi event can be generated either by the software watchdog timer, by the nmi input signal to the proce ssor, or by software. the nmi event is frequently used as a power-down indicator to initiate an orderly sh utdown of the system. ? exceptions C events that occur synchronously to program flow (in other words, the exception is taken before the instruction is allowed to complete). conditions such as data alignment violations and undefined instructions cause exceptions. ? interrupts C events that occur asynchronously to program flow. they are caused by inpu t signals, timers, and other peripherals, as well as by an explicit software instruction. core event controller (cec) the cec supports nine general-purpose interrupts (ivg15C7), in addition to the dedicated interrupt and exception events. of these general-purpose interrupts, the two lowest-priority interrupts (ivg15C14) are recomm ended to be reserved for software interrupt handlers. fo r more information, see the adsp-bf60x processor pr ogrammers reference. system event controller (sec) the sec manages the en abling, prioritization, and routing of events from each system interrup t or fault source. additionally, it provides notification and identi fication of the highest priority active system interrupt request to each core and routes system fault sources to its integrated fault management unit. trigger routing unit (tru) the tru provides system-level sequence control without core intervention. the tru maps trigge r masters (generators of trig- gers) to trigger slaves (receivers of triggers). slave endpoints can be configured to respond to tr iggers in various ways. common applications enabled by the tru include: ? automatically triggering the start of a dma sequence after a sequence from another dma channel completes ?software triggering ? synchronization of concurrent activities pin interrupts every port pin on the processor ca n request interrupts in either an edge-sensitive or a level-se nsitive manner with programma- ble polarity. interrupt functionality is decoupled from gpio operation. six system-level in terrupt channels (pint0C5) are reserved for this purpose. each of these interrupt channels can manage up to 32 interrupt pins. the assignment from pin to interrupt is not performed on a pi n-by-pin basis. rather, groups of eight pins (half ports) can be flexibly assigned to interrupt channels. every pin interrupt channel features a special set of 32-bit mem- ory-mapped registers that enab le half-port assignment and interrupt management. this includes masking, identification, and clearing of requests. these registers also enable access to the respective pin states and use of the interrupt latches, regardless of whether the interrupt is masked or not. most control registers feature multiple mmr address en tries to write-one-to-set or write-one-to-clear them individually. general-purpose i/o (gpio) each general-purpose port pin ca n be individually controlled by manipulation of the port control, status, and interrupt registers: ? gpio direction control register C specifies the direction of each individual gpio pin as input or output. ? gpio control and status regi sters C a write one to mod- ify mechanism allows any combination of individual gpio pins to be modified in a single instruction, without affecting the level of any other gpio pins. ? gpio interrupt mask register s C allow each individual gpio pin to function as an interrupt to the processor. gpio pins defined as inputs can be configured to generate hardware interrupts, while output pins can be triggered by software interrupts. ? gpio interrupt sensitivity registers C specify whether indi- vidual pins are level- or edge-sensitive and specifyif edge-sensitivewhether just the rising edge or both the ris- ing and falling edges of th e signal are significant. pin multiplexing the processor supports a flexible multiplexing scheme that mul- tiplexes the gpio pins with various peripherals. a maximum of 4 peripherals plus gpio function ality is shared by each gpio pin. all gpio pins ha ve a bypass path feature C that is, when the output enable and the input enable of a gpio pin are both active, the data signal before the pad driver is looped back to the receive path for the same gpio pin. for more information, see gp i/o multiplexing for 349-ball csp_bga on page 33. memory architecture the processor views memory as a single unified 4g byte address space, using 32-bit addresses. a ll resources, including internal memory, external memory, and i/o control registers, occupy separate sections of this common address space. the memory portions of this address space are arranged in a hierarchical structure to provide a good cost /performance balance of some very fast, low-latency core-acc essible memory as cache or sram, and larger, lower-cost an d performance interface-acces- sible memory systems. see figure 3 and figure 4 .
rev. 0 | page 7 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 figure 3. adsp-bf606 internal/external memory map
rev. 0 | page 8 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 figure 4. adsp-bf607/ADSP-BF608/adsp-bf609 internal/external memory map
rev. 0 | page 9 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 internal (core-accessible) memory the l1 memory system is th e highest-performance memory available to the blackf in processor cores. each core has its own private l1 memory. the modified har- vard architecture supports two concurrent 32-bit data accesses along with an instruction fetc h at full processor speed which provides high bandwidth processo r performance. in each core a 64k-byte block of data memory partners with an 80k-byte memory block for instruction storage. each data block is multi- banked for efficient data exchange through dma and can be configured as sram. alternativel y, 16k bytes of each block can be configured in l1 cache mode . the four-way set-associative instruction cache and the 2 two-wa y set-associative data caches greatly accelerate memory access performance, especially when accessing external memories. the l1 memory domain also fe atures a 4k-byte scratchpad sram block which is ideal for storing local va riables and the software stack. all l1 memory is protected by a multi-parity bit concept, regardless of whether the memory is operating in sram or cache mode. outside of the l1 domain, l2 and l3 memories are arranged using a von neumann topology. the l2 memory domain is a unified instruction and data memory and can hold any mixture of code and data required by the system design. the l2 memory domain is accessible by both blackfin cores through a dedicated 64-bit interface. it operates at sysclk frequency. the processor features up to 256k bytes of l2 sram which is ecc-protected and organized in eight banks. individual banks can be made private to any of the cores or the dma subsystem. there is also a 32k-byte single-bank rom in the l2 domain. it contains boot code and safety functions. static memory controller (smc) the smc can be programmed to control up to four banks of external memories or memory-ma pped devices, with very flexi- ble timing parameters. each bank occupies a 64m byte segment regardless of the size of the devi ce used, so that these banks are only contiguous if each is fu lly populated with 64m bytes of memory. dynamic memory controller (dmc) the dmc includes a controller that supports jesd79-2e com- patible double data rate ( ddr2) sdram and jesd209a low power ddr (lpddr) sdram devices. i/o memory space the processor does not define a separate i/o space. all resources are mapped through the fl at 32-bit address space. on- chip i/o devices have their cont rol registers mapped into mem- ory-mapped registers (mmrs) at addresses near the top of the 4g byte address space. these are separated into two smaller blocks, one which contains the control mmrs for all core func- tions, and the other which contains the registers needed for setup and control of the on-chip peripherals outside of the core. the mmrs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals. booting the processor has several mechan isms for automatically loading internal and external memory after a reset. the boot mode is defined by the sys_bmode input pins dedicated for this pur- pose. there are two categories of boot modes. in master boot modes, the processor actively load s data from parallel or serial memories. in slave boot modes, the processor receives data from external host devices. the boot modes are shown in table 2 . these modes are imple- mented by the sys_bmode bits of the reset configuration register and are sampled during power-on resets and software- initiated resets. video subsystem the following sections describe the components of the proces- sors video subsystem. these blocks are shown with blue shading in figure 1 on page 1 . video interconnect (vid) the video interconnect provides a connectivity matrix that interconnects the video subsystem: three ppis, the pixc, and the pvp. the interconnect uses a protocol to manage data transfer among these video peripherals. pipelined vision processor (pvp) the pvp engine provides hardware implementation of signal and image processing algorithms that are required for ? co-processing and pre-processing of monochrome video frames in adas applications, robotic systems, and other machine applications. the pvp works in conjunction with the blackfin cores. it is optimized for convolution and wavelet based object detection and classification, and tracking and verification algorithms. the pvp has the following processing blocks. ? four 5 5 16-bit convolution bl ocks optionally followed by down scaling ? a 16-bit cartesian-to-polar coordinate conversion block ? a pixel edge classifier that supports 1st and 2nd derivative modes ? an arithmetic unit with 32-bit addition, multiply and divide table 2. boot modes sys_bmode setting boot mode 000 no boot/idle 001 memory 010 rsi0 master 011 spi0 master 100 spi0 slave 101 reserved 110 lp0 slave 111 uart0 slave
rev. 0 | page 10 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 ? a 32-bit threshold block with 16 thresholds, a histogram, and run-length encoding ? two 32-bit integral blocks that support regular and diago- nal integrals ? an up- and down-scaling unit with independent scaling ratios for horizontal and vertical components ? input and output formatters for compatibility with many data formats, including bayer input format the pvp can form a pipe of all the constituent algorithmic modules and is dynamically reconfigurable to form different pipeline structures. the pvp supports the simultaneous processing of up to four data streams. the me mory pipe stream operates on data received by dma from any l1, l2, or l3 memory. the three camera pipe streams operate on a common input received directly from any of the three ppi inputs. optionally, the pixc can convert color data received by the ppi and forward luma values to the pvps monochrome engine. each stream has a dedicated dma output. this pr eprocessing concept ensures careful use of available power and bandwidth budgets and frees up the processor cores for other tasks. the pvp provides for direct core mmr access to all control/sta- tus registers. two hardware inte rrupts interface to the system event controller. for optimal perf ormance, the pvp allows reg- ister programming through its control dma interface, as well as outputting selected status re gisters through the status dma interface. this mechanism enables the pvp to automatically process job lists completely inde pendent of the blackfin cores. pixel compositor (pixc) the pixel compositor (pixc) provides image overlays with transparent-color support, alpha blending, and color space con- version capabilities for output to tft lcds and ntsc/pal video encoders. it provides all of the control to allow two data streams from two separate da ta buffers to be combined, blended, and converted into appropriate forms for both lcd panels and digital video outputs. the main image buffer pro- vides the basic backgr ound image, which is presented in the data stream. the over lay image buffer allows the user to add multiple foreground text, graphi cs, or video objects on top of the main image or video data stream. parallel peripheral interface (ppi) the processor provides up to thre e parallel peripheral interfaces (ppis), supporting data widths up to 24 bits. the ppi supports direct connection to tft lcd pa nels, parallel analog-to-digital and digital-to-analog converters, video encoders and decoders, image sensor modules and othe r general-purpose peripherals. the following features are supported in the ppi module: ? programmable data length: 8 bits, 10 bits, 12 bits, 14 bits, 16 bits, 18 bits, and 24 bits per clock. ? various framed, non-framed, and general-purpose operat- ing modes. frame syncs can be generated internally or can be supplied by an external device. ? itu-656 status word error de tection and correction for itu-656 receive modes and it u-656 preamble and status word decode. ? optional packing and unpackin g of data to/from 32 bits from/to 8 bits, 16 bits and 24 bi ts. if packing/unpacking is enabled, endianness can be configured to change the order of packing/unpackin g of bytes/words. ? rgb888 can be converted to rgb666 or rgb565 for trans- mit modes. ?various de-interleaving/inte rleaving modes for receiv- ing/transmitting 4:2:2 ycrcb data. ?configurable lcd data enable (den) output available on frame sync 3. processor safety features the adsp-bf60x processor has be en designed for functional safety applications. while the level of safety is mainly domi- nated by the system concept, the following primitives are provided by the devices to bu ild a robust safety concept. dual core supervision the processor has been implemented as dual-core devices to separate critical task s to large independency. software models support mutual supervision of th e cores in symmetrical fashion. multi-parity-bit-protected l1 memories in the processors l1 memory sp ace, whether sram or cache, each word is protected by multiple parity bits to detect the single event upsets that occur in all rams. this applies both to l1 instruction and data memory spaces. ecc-protected l2 memories error correcting codes (ecc) are used to correct single event upsets. the l2 memory is protected with a single error correct- double error detect (sec-ded ) code. by default ecc is enabled, but it can be disabled on a per-bank basis. single-bit errors are transparently corrected. dual-bit errors can issue a system event or fault if enabled. ecc protection is fully trans- parent to the user, even if l2 memory is read or written by 8-bit or 16-bit entities. crc-protected memories while parity bit and ecc protecti on mainly protect against ran- dom soft errors in l1 and l2 memory cells, the crc engines can be used to protect against system atic errors (pointer errors) and static content (instruction code ) of l1, l2 and even l3 memo- ries (ddr2, lpddr). the processors feature two crc engines which are embedded in the me mory-to-memory dma control- lers. crc check sums can be calc ulated or compared on the fly during memory transfers, or one or multiple memory regions can be continuously scrubbed by single dma work unit as per dma descriptor chain instructio ns. the crc engine also pro- tects data loaded during the boot process.
rev. 0 | page 11 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 memory protection the blackfin cores feature a memo ry protection concept, which grants data and/or instruction accesses from enabled memory regions only. a supervisor mode vs. user mode programming model supports dynamically varying access rights. increased flexibility in memory page si ze options supports a simple method of static memory partitioning. system protection all system resources and l2 memo ry banks can be controlled by either the processor cores, me mory-to-memory dma, or the system debug unit (sdu). a system protection unit (spu) enables write accesses to specific resources that are locked to any of four masters: core 0, core 1, memory dma, and the sys- tem debug unit. system protec tion is enabled in greater granularity for some modules (l2, sec and gpio controllers) through a global lock concept. watchpoint protection the primary purpose of watchpoints and hardware breakpoints is to serve emulator needs. when enabled, they signal an emula- tor event whenever user-defined system resources are accessed or a core executes from user -defined addresses. watchdog events can be configured such that they signal the events to the other blackfin core or to the fault management unit. dual watchdog the two on-chip watchdog timers each may supervise one blackfin core. bandwidth monitor all dma channels that operate in memory-to-memory mode (memory dma, pvp memory pipe dma, pixc dma) are equipped with a bandwidth monitor mechanism. they can sig- nal a system event or fault when transactions tend to starve because system buses are fully loaded with higher-priority traffic. signal watchdogs the eight general-purpose timers feature two new modes to monitor off-chip signals. the watchdog period mode monitors whether external signals toggle with a period within an expected range. the watchdog width mode monitors whether the pulse widths of external signals are in an expected range. both modes help to detect incorrect undesired toggling (or lack thereof) of ? system-level signals. up/down count mismatch detection the up/down counter can monitor external signal pairs, such as request/grant strobes. if the ed ge count mismatch exceeds the expected range, the up/down counte r can flag this to the proces- sor or to the fault management unit. fault management the fault management unit is part of the system event controller (sec). any system event, whether a dual-bit uncorrectable ecc error, or any peripheral status interrupt, can be defined as being a fault. additionally, the system events can be defined as an interrupt to the cores. if define d as such, the sec forwards the event to the fault management unit which may automatically reset the entire device for reb oot, or simply toggle the sys_ fault output pins to signal off-chip hardware. optionally, the fault management unit can delay the action taken via a keyed sequence, to provide a final chan ce for the blackfin cores to resolve the crisis and to prevent the fault action from being taken. additional processor peripherals the processor contains a rich set of peripherals connected to the core via several high-bandwidth buses, providing flexibility in system configuration as well as excellent overall system perfor- mance (see the block diagram on page 1 ). the processors contain high-speed serial and pa rallel ports, an interrupt con- troller for flexible management of interrupts from the on-chip peripherals or external sources, and power management control functions to tailor the performance and power characteristics of the processor and system to many application scenarios. the following sections describe additional peripherals that were not described in the previous sections. timers the processor includes several ti mers which are described in the following sections. general-purpose timers there is one gp timer unit and it provides eight general-pur- pose programmable timers. each timer has an external pin that can be configured either as a pulse width modulator (pwm) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. these timers can be synchronized to an external clock input on the tmrx pins, an external clock tmrclk input pin, or to the internal sclk0. the timer units can be used in conjunction with the uarts and the can controller to measure the width of the pulses in the data stream to provide a software auto-baud detect function for the respective serial channels. the timers can generate interrupts to the processor core, pro- viding periodic events for synchr onization to either the system clock or to external signals. timer events can also trigger other peripherals via the tru (for instance, to signal a fault). core timers each processor core al so has its own dedicated timer. this extra timer is clocked by the internal processor clock and is typically used as a system tick clock fo r generating periodic operating system interrupts. watchd og timers each core includes a 32-bit time r, which may be used to imple- ment a software watchdog function. a software watchdog can improve system availabi lity by forcing the processor to a known state, via generation of a hardwa re reset, nonmaskable interrupt (nmi), or general-purpose interrup t, if the timer expires before
rev. 0 | page 12 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 being reset by software. the pr ogrammer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. thereafter, the software must reload the counter before it counts to ze ro from the programmed value. this protects the system from remaining in an unknown state where software, which would no rmally reset the timer, has stopped running due to an external noise condition or software error. after a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the timer control register, which is set only upon a watchdog gener- ated reset. 3-phase pwm units the pulse width modulator (pwm ) module is a flexible and programmable wavefo rm generator. with minimal cpu inter- vention the pwm peripheral is capable of generating complex waveforms for motor control, pulse coded modulation (pcm), digital to analog conversion (dac), power switching and power conversion. the pwm modu le has 4 pwm pairs capable of 3-phase pwm generation for source inverters for ac induc- tion and dc brush less motors. the two 3-phase pwm generation units each feature: ? 16-bit center-based pwm generation unit ?programmable pwm pulse width ? single update mode with option for asymmetric duty ? programmable dead time and switching frequency ? twos-complement implementation which permits smooth transition to full on and full off states ? dedicated asynchronous pwm shutdown signal link ports four dma-enabled, 8-bit-wide link ports can connect to the link ports of other dsps or pr ocessors. link ports are bidirec- tional ports having eight data lines, an acknowledge line and a clock line. serial ports (sports) three synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as analog devices ad183x family of audio codecs, adcs, and dacs. the serial port s are made up of two data lines, a clock, and frame sync. the data lines can be pro- grammed to either transmit or receive and each data line has a dedicated dma channel. serial port data can be automa tically transferred to and from on-chip memory/external memory via dedicated dma chan- nels. each of the serial ports can work in conjunction with another serial port to provide tdm support. in this configura- tion, one sport provides two transmit signals while the other sport provides the two receive signals. the frame sync and clock are shared. serial ports operate in five modes: ? standard dsp serial mode ?multichannel (tdm) mode ?i 2 s mode ?packed i 2 s mode ? left-justified mode acm interface the adc control module (acm) provides an interface that synchronizes the controls betwee n the processor and an analog- to-digital converter (adc). the analog-to-digital conversions are initiated by the processor, based on external or internal events. the acm allows for flexible sche duling of sampling instants and provides precise sampling signals to the adc. figure 5 shows how to connect an external adc to the acm and one of the sports. the acm synchronizes the adc conversion process, generat- ing the adc controls, the adc conversion start signal, and other signals. the actual data acquisition from the adc is done by a peripheral such as a sport or a spi. the processor interfaces direct ly to many adcs without any glue logic required. general-purpose counters a 32-bit counter is provided that can operate in general-pur- pose up/down count modes and ca n sense 2-bit quadrature or binary codes as typically emitted by industrial drives or manual thumbwheels. count direction is either controlled by a level- sensitive input pin or by two edge detectors. figure 5. adc, acm, and sport connections sportx spt_ad1 spt_ad0 spt_clk spt_fs adc d out b d out a adsclk cs range sgl/diff a[2:0] acm acm_fs acm_clk acm_a4 acm_a3 acm_a[2:0] adsp-bf60x sport select mux
rev. 0 | page 13 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 a third counter input can provide flexible zero marker support and can alternatively be used to input the push-button signal of thumb wheels. all three pins have a programmable debouncing circuit. internal signals forwarded to ea ch general-purpos e timer enable these timers to measure the intervals between count events. boundary registers enable auto-z ero operation or simple system warning by interrupts when programmable count values are exceeded. serial peripheral interface (spi) ports the processors have two spi-co mpatible ports that allow the processor to communicate with multiple spi-compatible devices. in its simplest mode, the spi inte rface uses three pins for trans- ferring data: two data pins (master output-slave input, mosi, and master input-slave output, miso) and a clock pin (serial clock, spi_clk). a spi chip select input pin (spi_ss ) lets other spi devices select the processor, and seven spi chip select out- put pins (spi_sel7C1 ) let the processor select other spi devices. the spi select pins are reconfig ured general-purpose i/o pins. using these pins, the spi port provides a full-duplex, synchro- nous serial interface, which su pports both master/slave modes and multimaster environments. in a multi-master or multi-slave spi system, the mosi and miso data output pins can be configured to behave as open drain outputs (using the odm bi t) to prevent contention and possible damage to pin drivers. an external pull-up resistor is required on both the mosi and mi so pins when this option is selected. when odm is set and the spi is configured as a master, the mosi pin is three-stated when the data driven out on mosi is a logic-high. the mosi pin is not three-stated when the driven data is a logic-low. similarly, when odm is set and the spi is configured as a slave, the miso pin is three-stated if the data driven out on miso is a logic-high. the spi ports baud rate and clock phase/polarities are pro- grammable, and it has integrated dma channels for both transmit and receive data streams. uart ports the processors provide two full -duplex universa l asynchronous receiver/transmitter (uart) port s, which are fully compatible with pc-standard uarts. each uart port prov ides a simpli- fied uart interface to other pe ripherals or hosts, supporting full-duplex, dma-supported, asynch ronous transfers of serial data. a uart port includes support for five to eight data bits, and none, even, or odd parity. op tionally, an additional address bit can be transferred to inte rrupt only addressed nodes in multi-drop bus (mdb) systems. a frame is terminates by one, one and a half, two or two and a half stop bits. the uart ports support automatic hardware flow control through the clear to send (cts) input and request to send (rts) output with programmab le assertion fifo levels. to help support the local inte rconnect network (lin) proto- cols, a special command causes th e transmitter to queue a break command of programmable bit leng th into the transmit buffer. similarly, the number of stop bits can be extended by a pro- grammable inter-frame space. the capabilities of the uarts are further extended with sup- port for the infrared data association (irda?) serial infrared physical layer link specification (sir) protocol. twi controller interface the processors include a 2-wire interface (twi) module for providing a simple exchange method of control data between multiple devices. the twi modu le is compatible with the widely used i 2 c bus standard. the tw i module offers the capabilities of simultaneous master and slave operation and support for both 7-bit addressing and multimedia data arbitra- tion. the twi interface utilizes two pins for transferring clock (twi_scl) and data (twi_sda) and supports the protocol at speeds up to 400k bits/sec. the twi interface pins are compati- ble with 5 v logic levels. additionally, the twi module is fully compatible with serial camera control bus (sccb) functionality for easier control of various cmos camera sensor devices. removable storage interface (rsi) the removable storage interface (r si) controller acts as the host interface for multimedia cards (mmc), secure digital memory cards (sd), secure digital inpu t/output cards (sdio). the fol- lowing list describes the main features of the rsi controller. ? support for a single mmc , sd memory, sdio card ? support for 1-bit and 4-bit sd modes ? support for 1-bit, 4-bit, and 8-bit mmc modes ? support for emmc 4.3 embedded nand flash devices ? a ten-signal external interf ace with clock, command, and up to eight data lines ? card interface clock generation from sclk0 ? sdio interrupt and read wait features controller area network (can) a can controller implements the can 2.0b (active) protocol. this protocol is an asynchronous communications protocol used in both industrial and au tomotive control systems. the can protocol is well suited for control applications due to its capability to communicate reliab ly over a network. this is because the protocol incorporat es crc checking, message error tracking, and fault node confinement. the can controller offers the following features: ? 32 mailboxes (8 receive only , 8 transmit only, 16 configu- rable for receive or transmit). ? dedicated acceptance masks for each mailbox. ? additional data filtering on first two bytes. ? support for both the standard (11-bit) and extended (29- bit) identifier (i d) message formats.
rev. 0 | page 14 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 ? support for remote frames. ? active or passive network support. ? can wakeup from hibernation mode (lowest static power consumption mode). ? interrupts, including: tx complete, rx complete, error and global. an additional crystal is not required to supply the can clock, as the can clock is derived from a system clock through a pro- grammable divider. 10/100 ethernet mac the processor can directly connec t to a network by way of an embedded fast ethernet media access controller (mac) that supports both 10-baset (10m bits/sec) and 100-baset (100m bits/sec) operation. the 10/100 ethernet mac peripheral on the processor is fully compliant to the ieee 802.3-2002 standard and it provides programmable features designed to minimize supervision, bus use, or message processing by the rest of the processor system. some standard features are: ? support and rmii protocols for external phys ? full duplex and half duplex modes ? media access management (in half-duplex operation) ? flow control ? station management: generation of mdc/mdio frames for read-write access to phy registers some advanced features are: ? automatic checksum computat ion of ip header and ip payload fields of rx frames ? independent 32-bit descriptor-driven receive and transmit dma channels ? frame status delivery to me mory through dma, including frame completion semaphores for efficient buffer queue management in software ? tx dma support for separate descriptors for mac header and payload to eliminate buffer copy operations ? convenient frame alignment modes ? 47 mac management statistics counters with selectable clear-on-read behavi or and programmable interrupts on half maximum value ? advanced power management ? magic packet detection and wakeup frame filtering ? support for 802.3q tagged vlan frames ? programmable mdc clock rate and preamble suppression ieee 1588 support the ieee 1588 standard is a precision clock synchronization protocol for networked measurem ent and control systems. the processor includes hardware support for ieee 1588 with an integrated precision time protocol synchronization engine (ptp_tsync). this engine prov ides hardware assisted time stamping to improve the accuracy of clock synchronization between ptp nodes. the main features of the engine are: ? support for both ieee 1588-2002 and ieee 1588-2008 pro- tocol standards ? hardware assisted ti me stamping capable of up to 12.5 ns resolution ? lock adjustment ? automatic detection of ipv4 and ipv6 packets, as well as ptp messages ? multiple input clock sources (sclk0, rmii clock, external clock) ? programmable pulse per second (pps) output ? auxiliary snapshot to time stamp external events usb 2.0 on-the-go dual-r ole device controller the usb 2.0 otg dual-role device controller provides a low- cost connectivity solution for th e growing adoption of this bus standard in industrial applications, as well as consumer mobile devices such as cell phones, digi tal still cameras, and mp3 play- ers. the usb 2.0 controller allows these devices to transfer data using a point-to-point usb conn ection without the need for a pc host. the module can operat e in a traditional usb periph- eral-only mode as well as the host mode presented in the on- the-go (otg) supplement to the usb 2.0 specification. the usb clock (usb_clkin) is provided through a dedicated external crystal or crystal oscillator. the usb on-the-go dual-role device controller includes a phase locked loop with programm able multipliers to generate the necessary internal clocking frequency for usb. power and clock management the processor provides four operating modes, each with a dif- ferent performance/power profil e. when configured for a 0 v internal supply voltage (v dd_int ), the processor enters the hiber- nate state. control of clocki ng to each of the processor peripherals also reduces power consumption. see table 5 for a summary of the power se ttings for each mode. crystal oscillator (sys_xtal) the processor can be clocked by an external crystal, ( figure 6) a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. if an external clock is used, it should be a ttl compatible signal and must not be halted, changed, or operated below the specified fr equency during normal opera- tion. this signal is connecte d to the processors sys_clkin pin. when an external clock is used, the sys_xtal pin must be left unconnected. alternatively, because the processor includes an on-chip oscillator circuit, an external crystal may be used. for fundamental frequency operat ion, use the circuit shown in figure 6 . a parallel-resonant, fundamental frequency, micro- processor grade crystal is conn ected across the sys_clkin and xtal pins. the on-chip resistance between sys_clkin and the xtal pin is in the 500 k ra nge. further parallel resistors are typically not recommended.
rev. 0 | page 15 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 the two capacitors and the series resistor shown in figure 6 fine tune phase and amplitude of the sine frequency. the capacitor and resistor va lues shown in figure 6 are typical values only. the capacitor values are dependent upon the crystal manufac- turers load capacitance recommendations and the pcb physical layout. the resistor value depends on the drive level specified by the crystal manufacturer. the user should verify the customized values based on careful investigat ions on multiple devices over temperature range. a third-overtone crystal can be used for frequencies above ? 25 mhz. the circuit is then modified to ensure crystal operation only at the third overtone by ad ding a tuned inductor circuit as shown in figure 6 . a design procedure fo r third-overtone oper- ation is discussed in detail in application note (ee-168) using third overtone crystals with the adsp-218x dsp on the ana- log devices website (www.analog.com)use site search on ? ee-168. usb crystal oscillator the usb can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. if an external cl ock is used, it should be a ttl compatible signal and must not be halted, changed, or operated below the specified frequency during normal operation. this signal is connected to the proc essors usb_xtal pin. alterna- tively, because the processor in cludes an on-chip oscillator circuit, an external crystal may be used. for fundamental frequency operat ion, use the circuit shown in figure 7 . a parallel-resonant, fund amental frequency, micro- processor grade crystal is connected between the usb_xtal pin and ground. a load capacitor is placed in parallel with the crystal. the combined capacitive value of the board trace para- sitic, the case capacitance of the crystal (from crystal manufacturer) and the parallel ca pacitor in the diagram should be in the range of 8 pf to 15 pf. the crystal should be chosen so that its rated load capacitance matches the nominal total capacitance on this node. a series resistor may be added between the usb_xtal pin and the par- allel crystal and capacitor comb ination, in order to further reduce the drive level of the crystal. the parallel capacitor and the series resistor shown in figure 7 fine tune phase and amplitude of the sine frequency. the capac- itor and resistor values shown in figure 7 are typical values only. the capacitor values are dependent upon the crystal man- ufacturers load capacitance recommendations and the pcb physical layout. the resistor va lue depends on the drive level specified by the crystal manufact urer. the user should verify the customized values based on careful investigations on multiple devices over temperature range. clock generation the clock generation unit (cgu ) generates all on-chip clocks and synchronization signals. mu ltiplication factors are pro- grammed to the pll to define the pllclk frequency. programmable values divide the pllclk frequency to generate the core clock (cclk), the syst em clocks (sysclk, sclk0 and sclk1), the lpddr or ddr2 cl ock (dclk) and the output clock (oclk). this is illustrated in figure 8 on page 53 . writing to the cgu control registers does not affect the behav- ior of the pll immediately. regi sters are first programmed with a new value, and the pll logic ex ecutes the changes so that it transitions smoothly from the current conditions to the new ones. sys_clkin oscillations start when power is applied to the v dd_ ext pins. the rising edge of sys_hwrst can be applied after all voltage supplies are within specifications (see operating condi- tions on page 52 ), and sys_clkin oscillations are stable. clock out/external clock the sys_clkout output pin has programmable options to output divided-down versions of the on-chip clocks. by default, the sys_clkout pin drives a buffered version of the sys_ clkin input. clock generation faults (for example pll unlock) may trigger a reset by hard ware. the clocks shown in table 3 can be outputs from sys_clkout. figure 6. external crystal connection sys_clkin to pll circuitry for overtone operation only: note: values marked with * must be customized, depending on the crystal and layout. please analyze carefully. for frequencies above 33 mhz, the suggested capacitor value of 18pf should be treated as a maximum, and the suggested 5(6,67259$/8(6+28/'%(5('8&('72 18 pf* 18 pf * * blackfin sys_xtal figure 7. external usb crystal connection to usb pll blackfin 2 5-12 pf 1, 2 notes: 1. capacitance value shown includes board parasitics 2. values are a preliminary estimate.
rev. 0 | page 16 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 power management as shown in table 4 , the processor supports five different power domains, which maximizes flexibility while maintaining com- pliance with industry standards and conventions. there are no sequencing requirements for the various power domains, but all domains must be powered ac cording to the appropriate specifi- cations table for processor operating conditions; even if the feature/peripheral is not used. the dynamic power management feature of the processor allows the processors core clock frequency (f cclk ) to be dynam- ically controlled. the power dissipated by a processo r is largely a function of its clock frequency and the square of the operating voltage. for example, reducing the clock freq uency by 25% re sults in a 25% reduction in dynamic power dissipation. full-on operating modemaximum performance in the full-on mode, the pll is enabled and is not bypassed, providing capability for maximum operational frequency. this is the power-up default execut ion state in which maximum per- formance can be achieved. the processor cores and all enabled peripherals run at full speed. active operating modemoderate dynamic power savings in the active mode, the pll is enabled but bypassed. because the pll is bypassed, the processors core clocks and system clocks run at the input clock (sys_clkin) frequency. dma access is available to appropriately configured l1 memories. for more information about pl l controls, see the dynamic power management chapter in the adsp-bf60x blackfin pro- cessor hardware reference . see table 5 for a summary of the powe r settings for each mode. deep sleep operating modemaximum dynamic power savings the deep sleep mode maximizes dynamic power savings by dis- abling the clocks to the proce ssor core and to all synchronous peripherals. asynchronous periph erals may still be running but cannot access internal reso urces or external memory. hibernate statemaximum static power savings the hibernate state maximizes stat ic power savings by disabling the voltage and clocks to the processor cores and to all of the peripherals. this setting signal s the external voltage regulator supplying the v dd_int pins to shut off using the sys_ extwake signal, which provides the lowest static power dissi- pation. any critical information st ored internally (for example, memory contents, register contents, and other information) must be written to a non-volatile storage device prior to remov- ing power if the processor state is to be preserved. since the v dd_ext pins can still be supplied in this mode, all of the external pins three-state, unless otherwise specified. this allows other devices that may be connected to the processor to still have power applied without drawing unwanted current. reset control unit reset is the initial state of th e whole processor or one of the cores and is the result of a hardware or software triggered event. in this state, all control registers are set to their default values and functional units are idle. ex iting a full system reset starts with core-0 only being ready to boot. exiting a core-n only reset starts with this core-n being ready to boot. the reset control unit (rcu) co ntrols how all the functional units enter and exit reset. differences in functional require- ments and clocking constraints define how reset signals are generated. programs must guarantee that none of the reset functions puts the system into an undefined state or causes resources to stall. th is is particularly important when only one of the cores is reset (programs must ensure that there is no pending system activity involving the core that is being reset). table 3. clock dividers clock source divider cclk (core clock) by 4 sysclk (system clock) by 2 sclk0 (system clock for pvp, all peripherals not covered by sclk1) none sclk1 (system clock for sports, spi, acm) none dclk (lpddr/ddr2 clock) by 2 oclk (output clock) programmable clkbuf none, direct from sys_clkin table 4. power domains power domain v dd range all internal logic v dd_int ddr2/lpddr v dd_dmc usb v dd_usb thermal diode v dd_td all other i/o (includes sys, jtag, and ports pins) v dd_ext table 5. power settings mode/state pll pll ? bypassed f cclk f sysclk , ? f dclk , ? f sclk0 , ? f sclk1 core ? power full on enabled no enabled enabled on active enabled/ ? disabled yes enabled enabled on deep sleep disabled disabled disabled on hibernate disabled disabled disabled off
rev. 0 | page 17 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 from a system perspective reset is defined by both the reset tar- get and the reset source as described below. target defined: ? hardware reset C all functional units are set to their default states without exception. history is lost. ? system reset C all functional units except the rcu are set to their default states. ? core-n only reset C affects co re-n only. the system soft- ware should guarantee that the core in reset state is not accessed by any bus master. source defined: ? hardware reset C the sys_hwrst input signal is asserted active (pulled down). ? system reset C may be triggered by software (writing to the rcu_ctl register) or by another functional unit such as the dynamic power management (dpm) unit (hibernate) or any of the system event co ntroller (sec), trigger routing unit (tru), or emulator inputs. ? core-n-only reset C triggered by software. ? trigger request (peripheral). voltage regulation the processor requires an external voltage regulator to power the v dd_int pins. to reduce standby power consumption, the external voltage regulator can be signaled through sys_ extwake to remove power from the processor core. this sig- nal is high-true for power-up and may be connected directly to the low-true shut-down input of many common regulators. while in the hibernate state, all external supply pins (v dd_ext , v dd_usb , v dd_dmc ) can still be powered, eliminating the need for external buffers. the external vo ltage regulator can be activated from this power down state by asserting the sys_hwrst pin, which then initiates a boot sequence. sys_extwake indicates a wakeup to the external voltage regulator. system debug the processor includes various fe atures that allow for easy sys- tem debug. these are described in the following sections. system watchpoint unit the system watchpoint unit (s wu) is a single module which connects to a single system bu s and provides for transaction monitoring. one swu is attached to the bus going to each sys- tem slave. the swu provides po rts for all system bus address channel signals. each swu contains four match groups of regis- ters with associated hardware . these four swu match groups operate independently, but share common event (interrupt, trigger and others) outputs. system debug unit the system debug unit (sdu) provides ieee-1149.1 support through its jtag interface. in ad dition to traditional jtag fea- tures, present in legacy blackf in products, the sdu adds more features for debugging the chip without halting the core processors. development tools analog devices supports its proce ssors with a complete line of software and hardware development tools, including integrated development environments (which include crosscore ? embed- ded studio and/or visualdsp++ ? ), evaluation products, emulators, and a wide variety of software add-ins. integrated development environments (ides) for c/c++ software writing and editing, code generation, and debug support, analog devices offers two ides. the newest ide, crosscore embe dded studio, is based on the eclipse tm framework. supporting most analog devices proces- sor families, it is the ide of choice for future processors, including multicore devices. crosscore embedded studio seamlessly integrates available so ftware add-ins to support real time operating systems, file systems, tcp/ip stacks, usb stacks, algorithmic software modules, and evaluation hardware board support packages. for more information visit www.analog.com/cces . the other analog devices ide, visualdsp++, supports proces- sor families introduced prior to the release of crosscore embedded studio. this ide incl udes the analog devices vdk real time operating system and an open source tcp/ip stack. for more information visit www.analog.com/visualdsp . note that visualdsp++ will not suppo rt future analog devices processors. ez-kit lite evaluation board for processor evaluation, analog devices provides wide range of ez-kit lite ? evaluation boards. incl uding the processor and key peripherals, the evaluation board also supports on-chip emulation capabilities and other evaluation and development features. also available are various ez-extenders ? , which are daughter cards delivering additional specialized functionality, including audio and video processing. for more information visit www.analog.com and search on ezkit or ezextender. ez-kit lite evaluation kits for a cost-effective way to lear n more about developing with analog devices processors, analog devices offer a range of ez- kit lite evaluation kits. each evaluation kit includes an ez-kit lite evaluation board, directions for downloading an evaluation version of the available ide(s), a usb cable, and a power supply. the usb controller on the ez-kit lite board connects to the usb port of the users pc, enab ling the chosen ide evaluation suite to emulate the on-board pr ocessor in-circuit. this permits the customer to download, execut e, and debug programs for the ez-kit lite system. it also su pports in-circuit programming of the on-board flash device to store user-specific boot code, enabling standalone operatio n. with the full version of
rev. 0 | page 18 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 crosscore embedded studio or visualdsp++ installed (sold separately), engineers can deve lop software for supported ez- kits or any custom system util izing supported analog devices processors. software add-ins for cr osscore embedded studio analog devices offers software add-ins which seamlessly inte- grate with crosscore embedded stud io to extend its capabilities and reduce development time. add-ins include board support packages for evaluation hardwa re, various middleware pack- ages, and algorithmic modules. documentation, help, configuration dialogs, and coding examples present in these add-ins are viewable through th e crosscore embedded studio ide once the add-in is installed. board support packages for evaluation hardware software support for the ez-kit lite evaluation boards and ez- extender daughter cards is prov ided by software add-ins called board support packages (bsps). the bsps contain the required drivers, pertinent release notes, and select example code for the given evaluation hardware. a downlo ad link for a specific bsp is located on the web page for the associated ez-kit or ez- extender product. the link is found in the product download area of the product web page. middleware packages analog devices separately offers middleware add-ins such as real time operating systems, file systems, usb stacks, and tcp/ip stacks. for more information see the following web pages: ? www.analog.com/ucos3 ? www.analog.com/ucfs ? www.analog.com/ucusbd ? www.analog.com/lwip algorithmic modules to speed development, analog de vices offers add-ins that per- form popular audio and video processing algorithms. these are available for use with both cr osscore embedded studio and visualdsp++. for more information visit www.analog.com and search on blackfin software modules. designing an emulator-compatible dsp board (target) for embedded system test and de bug, analog devices provides a family of emulators. on each jtag dsp, analog devices sup- plies an ieee 1149.1 jtag test access port (tap). in-circuit emulation is facilitated by use of this jtag interface. the emu- lator accesses the processors internal features via the processors tap, allowing the de veloper to load code, set break- points, and view variables, memory, and registers. the processor must be halted to se nd data and commands, but once an operation is completed by the emulator, the dsp system is set to run at full speed with no im pact on system timing. the emu- lators require the target board to include a header that supports connection of the dsps jtag port to the emulator. for details on target board desi gn issues including mechanical layout, single processor connection s, signal buffering, signal ter- mination, and emulator pod logic, see the ee-68: analog devices jtag emulation technical reference on the analog devices website ( www.analog.com )use site search on ee-68. this document is updated regularly to keep pace with improvements to emulator support. additional information the following publications that describe the adsp-bf606/ adsp-bf607/ADSP-BF608/adsp -bf609 processors (and related processors) can be ordered from any analog devices sales office or accessed electronically on our website: ? getting started with blackfin processors ? adsp-bf60x blackfin proc essor hardware reference ? blackfin processor programming reference ? adsp-bf60x blackfin processor anomaly list related signal chains a signal chain is a series of signal-conditioning electronic com- ponents that receive input (data acquired from sampling either real-time phenomena or from stor ed data) in tandem, with the output of one portion of the ch ain supplying input to the next. signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. for more information about this term and related topics, see the signal chain entry in the glossary of ee terms on the analog devices website. analog devices eases signal proc essing system development by providing signal processing comp onents that are designed to work together well. a tool fo r viewing relationships between specific applications and related components is available on the www.analog.com website. the application signal chains page in the circuits from the lab tm site ( http:\\www.analog.com\circuits ) provides: ? graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications ? drill down links for components in each chain to selection guides and application information ? reference designs applying be st practice design techniques
rev. 0 | page 19 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 adsp-bf60x detailed signal descriptions table 6 provides a detailed description of each signal. table 6. detailed signal descriptions signal name direction description acm_an output adc control signals function varies by mode. acm_clk output clock sclk derived clock for connecting to an adc. acm_fs output frame sync typically used as an adc chip select. acm_tn input external trigger n input for external trigger events. can_rx input receive typically an external can transceiver's rx output. can_tx output transmit typically an external can transceiver's tx input. cnt_dg input count down and gate depending on the mode of operation th is input acts either as a count down signal or a gate signal. count down: this input causes the gp counter to decrement. gate: stops the gp counter from incrementing or decrementing. cnt_ud input count up and direction depending on the mode of operation this input acts either as a count up signal or a direction signal. count up: this input causes the gp counter to increment. direction: selects whether the gp counter is incrementing or decrementing. cnt_zm input count zero marker input that connects to the zero marker output of a rotary device or detects the pressing of a push button. dmc_ann output address n address bus. dmc_ban output bank address input n defines which internal bank an activa te, read, write, or precharge command is being applied to on the dynamic memory. also de fines which mode register s (mr, emr, emr2, and/or emr3) are loaded during the load mode register command. dmc_cas output column address strobe defines the operation for external dynamic memory to perform in conjunction with other dmc command signals. connect to the cas input of dynamic memory. dmc_ck output clock (complement) complement of dmc_ck. dmc_ck output clock outputs dclk to external dynamic memory. dmc_cke output clock enable active high clock enables. connects to the dynamic memorys cke input. dmc_csn output chip select n commands are recognized by the memory only when this signal is asserted. dmc_dqnn i/o data n bidirectional data bus. dmc_ldm output data mask for lower byte mask for dmc_dq07:dmc_dq00 write data when driven high. sampled on both edges of the data strobe by the dynamic memory. dmc_ldqs i/o data strobe for lower byte (complement) complement of ldqs. not used in single-ended mode. dmc_ldqs i/o data strobe for lower byte dmc_dq07:dmc_dq00 data strobe. output with write data. input with read data. may be single-ended or differ ential depending on register settings. dmc_odt output on-die termination enables dynamic memory termination resistances when driven high (assuming the memory is properly configured). odt is enabled/disabled regardless of read or write commands. dmc_ras output row address strobe defines the operation for external dynamic memory to perform in conjunction with other dmc command signals. connect to the ras input of dynamic memory. dmc_udm output data mask for upper byte mask for dmc_dq15:dmc_dq08 write data when driven high. sampled on both edges of the data strobe by the dynamic memory. dmc_udqs i/o data strobe for upper byte (complement) complement of udqs. not used in single-ended mode. dmc_udqs i/o data strobe for upper byte dmc_dq15:dmc_dq08 data strobe. output with write data. input with read data. may be single-ended or differ ential depending on register settings. dmc_we output write enable defines the operation for external dynamic memory to perform in conjunction with other dmc command signals. connect to the we input of dynamic memory.
rev. 0 | page 20 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 eth_crs input carrier sense/rmii receive data valid multiplexed on alternate clock cycles. crs: asserted by the phy when either the transmit or receive medium is not idle. de-asserted when both are idle. rxdv: asserted by the phy when the data on rxdn is valid. eth_mdc output management channel clock clocks the mdc input of the phy. eth_mdio i/o management channel serial data bidirectional data bus for phy control. eth_ptpauxin input ptp auxiliary trigger input assert this signal to take an auxiliary snapshot of the time and store it in the auxiliary time stamp fifo. eth_ptpclkin input ptp clock input optional external ptp clock input. eth_ptppps output ptp pulse-per-second output when the advanced time stamp feature is enabled, this signal is asserted based on the pps mode selected. otherwise, ptppps is asserted every time the seconds counter is incremented. eth_refclk input reference clock externally supplied ethernet clock. eth_rxdn input receive data n receive data bus. eth_txdn output transmit data n transmit data bus. eth_txen i/o transmit enable when asserted indicates that the data on txdn is valid. jtg_emu output emulation output jtag emulation flag. jtg_tck input clock jtag test access port clock. jtg_tdi input serial data in jtag test access port data input. jtg_tdo output serial data out jtag test access port data output. jtg_tms input mode select jtag test access port mode select. jtg_trst input reset jtag test access port reset. lp_ack i/o acknowledge provides handshaking. when the link port is configured as a receiver, ack is an output. when the link port is configured as a transmitter, ack is an input. lp_clk i/o clock when the link port is configured as a receiver, clk is an input. when the li nk port is configured as a transmitter, clk is an output. lp_dn i/o data n data bus. input when receiv ing, output when transmitting. ppi_clk i/o clock input in external clock mode, output in internal clock mode. ppi_dnn i/o data n bidirectional data bus. ppi_fs1 i/o frame sync 1 (hsync) behavior depends on ppi mode. see the ppi chapter in the processor hardware reference for more details. ppi_fs2 i/o frame sync 2 (vsync) behavior depends on ppi mode. see the ppi chapter in the processor hardware reference for more details. ppi_fs3 i/o frame sync 3 (field) behavior depends on ppi mode. see the ppi chapter in the processor hardware reference for more details. pwm_ah output channel a high side high side drive signal. pwm_al output channel a low side low side drive signal. pwm_bh output channel b high side high side drive signal. pwm_bl output channel b low side low side drive signal. pwm_ch output channel c high side high side drive signal. pwm_cl output channel c low side low side drive signal. pwm_dh output channel d high side high side drive signal. pwm_dl output channel d low side low side drive signal. pwm_sync input pwm external sync this input is for an externally generated sync signal. if the sync signal is internally generated no connection is necessary. pwm_tripn input shutdown input n when asserted the selected pwm channel outputs are shut down immediately. px_nn i/o position n general purpose input/output. see the gp ports chapter in the processor hardware reference for programming information. table 6. detailed signal descriptions (continued) signal name direction description
rev. 0 | page 21 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 rsi_clk output clock the clock signal applied to the connected device from the rsi. rsi_cmd i/o command used to send commands to and receive responses from the connected device. rsi_dn i/o data n bidirectional data bus. smc_aben output byte enable n indicate whether the lower or upper byte of a memory is being accessed. when an asynchronous write is made to the up per byte of a 16-bit memory, smc_abe1 =0 and smc_abe0 =1. when an asynchronous write is made to the lower byte of a 16-bit memory, smc_abe1 =1 and smc_abe0 =0. smc_amsn output memory select n typically connects to the chip select of a memory device. smc_ann output address n address bus. smc_aoe output output enable asserts at the beginning of the setup period of a read access. smc_ardy input asynchronous ready flow control signal used by memory devices to indicate to the smc when further transactions may proceed. smc_are output read enable asserts at the beginning of a read access. smc_awe output write enable asserts for the duration of a write access period. smc_bg output bus grant output used to indicate to an external device that it has been granted control of the smc buses. smc_bgh output bus grant hang output used to indicate that the smc has a pending transaction which requires control of the bus to be restored before it can be completed. smc_br input bus request input used by an external device to indicate that it is requesting control of the smc buses. smc_dnn i/o data n bidirectional data bus. smc_norclk output nor clock clock for synchronous burst mode. smc_nordv output nor data valid asserts for the duration of a synchronous burst mode read setup period. smc_norwt input nor wait flow control signal used by memory devices in synchronous burst mode to indicate to the smc when further transactions may proceed. spi_clk i/o clock input in slave mode, output in master mode. spi_d2 i/o data 2 used to transfer serial data in quad mode. open drain in odm mode. spi_d3 i/o data 3 used to transfer serial data in quad mode. open drain in odm mode. spi_miso i/o master in, slave out used to transfer serial da ta. operates in the same direction as spi_mosi in dual and quad modes. open drain in odm mode. spi_mosi i/o master out, slave in used to transfer serial data. operates in the same direction as spi_miso in dual and quad modes. open drain in odm mode. spi_rdy i/o ready optional flow signal. output in slave mode, input in master mode. spi_seln output slave select output n used in master mode to enable the desired slave. spi_ss input slave select input slave mode: acts as the slave select input. master mode: optionally serves as an error detection input for the spi when there are multiple masters. spt_aclk i/o channel a clock data and frame sync are driven/sampled with respect to this clock. this signal can be either internally or externally generated. spt_ad0 i/o channel a data 0 primary bidirectional data i/o. this signal can be configured as an output to transmit serial data, or as an input to receive serial data. spt_ad1 i/o channel a data 1 secondary bidirectional data i/o. this si gnal can be configured as an output to transmit serial data, or as an input to receive serial data. spt_afs i/o channel a frame sync the frame sync pulse initiates shifting of serial data. this signal is either generated internally or externally. spt_atdv output channel a transmit data valid this signal is optional and only active when sport is configured in multi-channel transmit mode. it is asserted during enabled slots. spt_bclk i/o channel b clock data and frame sync are driven/sampled with respect to this clock. this signal can be either internally or externally generated. spt_bd0 i/o channel b data 0 primary bidirectional data i/o. this signal can be configured as an output to transmit serial data, or as an input to receive serial data. table 6. detailed signal descriptions (continued) signal name direction description
rev. 0 | page 22 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 spt_bd1 i/o channel b data 1 secondary bidirectional data i/o. this signal can be configured as an output to transmit serial data, or as an input to receive serial data. spt_bfs i/o channel b frame sync the frame sync pulse initiates shifting of serial data. this signal is either generated internally or externally. spt_btdv output channel b transmit data valid this signal is optional and only active when sport is configured in multi-channel transmit mode. it is asserted during enabled slots. sys_bmoden input boot mode control n selects the boot mode of the processor. sys_clkin input clock/crystal input connect to an external clock source or crystal. sys_clkout output processor clock output outputs internal clocks. clocks may be divided down. see the cgu chapter in the processor hardware reference for more details. sys_extwake output external wake control drives low during hibernate and high all other times. typically connected to the enable input of the voltage regulator controlling the v dd_int supply. sys_fault i/o complementary fault complement of sys_fault. sys_fault i/o fault indicates internal faults or senses extern al faults depending on the operating mode. sys_hwrst input processor hardware reset control resets the device when asserted. sys_idlen output core n idle indicator when low indicates that core n is in idle mode or being held in reset. sys_nmi input non-maskable interrupt priority depends on the core that receives the interrupt. see the processor hardware and programming references for more details. sys_pwrgd input power good indicator when high it indicates to the processor that the v dd_int level is within specifica- tions such that it is safe to begin booting upon return from hibernate. sys_resout output reset output indicates that the device is in the reset state. sys_sleep output processor sleep indicator when low indicates that the processor is in the deep sleep power saving mode. sys_tda input thermal diode anode may be used by an external temperatur e sensor to measure the die temperature. sys_tdk input thermal diode cathode may be used by an external temp erature sensor to measure the die temperature. sys_xtal output crystal output drives an external crystal. must be left un connected if an external clock is driving clkin. tmr_acin input alternate capture input n provides an additional input for widcap, watchdog, and pinint modes. tmr_aclkn input alternate clock n provides an additional time base for use by an individual timer. tmr_clk input clock provides an additional global time base for use by all the gp timers. tmr_tmrn i/o timer n the main input/output signal for each timer. twi_scl i/o serial clock clock output when master, clock input when slave. twi_sda i/o serial data receives or transmits data. uart_cts input clear to send flow control signal. uart_rts output request to send flow control signal. uart_rx input receive receive input. typically connects to a transceiver that meets the electrical requirements of the device being communicated with. uart_tx output transmit transmit output. typically connects to a transcei ver that meets the electrical requirements of the device being communicated with. usb_clkin input clock/crystal input this clock input is multiplied by a pll to form the usb clock. see universal serial bus (usb) on-the-goreceive and transmit timing for frequency/tolerance information. usb_dm i/o data C bidirectional differential data line. usb_dp i/o data + bidirectional differential data line. usb_id input otg id senses whether the controller is a host or device . this signal is pulled low when an a-type plug is sensed (signifying that the usb controller is the a device), but the input is high when a b-type plug is sensed (signifying that the usb controller is the b device). usb_vbc output vbus control controls an external voltage source to supply vbus when in host mode. may be configured as open drain. pola rity is configurable as well. usb_vbus i/o bus voltage connects to bus voltage in host and device modes. table 6. detailed signal descriptions (continued) signal name direction description
rev. 0 | page 23 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 349-ball csp_bga signal descriptions the processors' pin definitions ar e shown in the table. the col- umns in this table provide the following information: ? signal name: the signal name column in the table includes the signal name for every pin. ? description: the description column in the table provides a verbose (descriptive) name for the signal. ? port: the general-purpose i/o port column in the table shows whether or not the signal is multiplexed with other signals on a general-purpose i/o port pin. ? pin name: the pin name column in the table identifies the name of the package pin (at po wer-on reset) on which the signal is located (if a single fu nction pin) or is multiplexed (if a general-purpose i/o pin). table 7. adsp-bf60x 349-ball csp_bga signal descriptions signal name description port pin name acm0_a0 acm0 address 0 f pf_14 acm0_a1 acm0 address 1 f pf_15 acm0_a2 acm0 address 2 f pf_12 acm0_a3 acm0 address 3 f pf_13 acm0_a4 acm0 address 4 f pf_10 acm0_clk acm0 clock e pe_04 acm0_fs acm0 frame sync e pe_03 acm0_t0 acm0 external trigger 0 e pe_08 acm0_t1 acm0 external trigger 1 g pg_05 can0_rx can0 receive g pg_04 can0_tx can0 transmit g pg_01 cnt0_dg cnt0 count down and gate g pg_12 cnt0_ud cnt0 count up and direction g pg_11 cnt0_zm cnt0 count zero marker g pg_07 dmc0_a00 dmc address 0 not muxed dmc0_a00 dmc0_a01 dmc address 1 not muxed dmc0_a01 dmc0_a02 dmc address 2 not muxed dmc0_a02 dmc0_a03 dmc address 3 not muxed dmc0_a03 dmc0_a04 dmc address 4 not muxed dmc0_a04 dmc0_a05 dmc address 5 not muxed dmc0_a05 dmc0_a06 dmc address 6 not muxed dmc0_a06 dmc0_a07 dmc address 7 not muxed dmc0_a07 dmc0_a08 dmc address 8 not muxed dmc0_a08 dmc0_a09 dmc address 9 not muxed dmc0_a09 dmc0_a10 dmc address 10 not muxed dmc0_a10 dmc0_a11 dmc address 11 not muxed dmc0_a11 dmc0_a12 dmc address 12 not muxed dmc0_a12 dmc0_a13 dmc address 13 not muxed dmc0_a13 dmc0_ba0 dmc bank address input 0 not muxed dmc0_ba0 dmc0_ba1 dmc bank address input 1 not muxed dmc0_ba1 dmc0_ba2 dmc bank address input 2 not muxed dmc0_ba2 dmc0_cas dmc column address strobe not muxed dmc0_cas dmc0_ck dmc clock not muxed dmc0_ck dmc0_cke dmc clock enable not muxed dmc0_cke dmc0_ck dmc clock (complement) not muxed dmc0_ck dmc0_cs0 dmc chip select 0 not muxed dmc0_cs0
rev. 0 | page 24 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 dmc0_dq00 dmc data 0 not muxed dmc0_dq00 dmc0_dq01 dmc data 1 not muxed dmc0_dq01 dmc0_dq02 dmc data 2 not muxed dmc0_dq02 dmc0_dq03 dmc data 3 not muxed dmc0_dq03 dmc0_dq04 dmc data 4 not muxed dmc0_dq04 dmc0_dq05 dmc data 5 not muxed dmc0_dq05 dmc0_dq06 dmc data 6 not muxed dmc0_dq06 dmc0_dq07 dmc data 7 not muxed dmc0_dq07 dmc0_dq08 dmc data 8 not muxed dmc0_dq08 dmc0_dq09 dmc data 9 not muxed dmc0_dq09 dmc0_dq10 dmc data 10 not muxed dmc0_dq10 dmc0_dq11 dmc data 11 not muxed dmc0_dq11 dmc0_dq12 dmc data 12 not muxed dmc0_dq12 dmc0_dq13 dmc data 13 not muxed dmc0_dq13 dmc0_dq14 dmc data 14 not muxed dmc0_dq14 dmc0_dq15 dmc data 15 not muxed dmc0_dq15 dmc0_ldm dmc data mask for lower byte not muxed dmc0_ldm dmc0_ldqs dmc data strobe for lower byte not muxed dmc0_ldqs dmc0_ldqs dmc data strobe for lower byte (complement) not muxed dmc0_ldqs dmc0_odt dmc on-die termin ation not muxed dmc0_odt dmc0_ras dmc row address strobe not muxed dmc0_ras dmc0_udm dmc data mask for upper byte not muxed dmc0_udm dmc0_udqs dmc data strobe for upper byte not muxed dmc0_udqs dmc0_udqs dmc data strobe for upper byte (complement) not muxed dmc0_udqs dmc0_we dmc write enable not muxed dmc0_we eth0_crs emac0 carrier sense/rmii receive data valid c pc_05 eth0_mdc emac0 management channel clock c pc_06 eth0_mdio emac0 management channel serial data c pc_07 eth0_ptppps emac0 ptp pulse-per-second output b pb_15 eth0_refclk emac0 reference clock b pb_14 eth0_rxd0 emac0 receive data 0 c pc_00 eth0_rxd1 emac0 receive data 1 c pc_01 eth0_txd0 emac0 transmit data 0 c pc_02 eth0_txd1 emac0 transmit data 1 c pc_03 eth0_txen emac0 transmit enable b pb_13 eth1_crs emac1 carrier sense/rmii receive data valid e pe_13 eth1_mdc emac1 management channel clock e pe_10 eth1_mdio emac1 management channel serial data e pe_11 eth1_ptppps emac1 ptp pulse-per-second output c pc_09 eth1_refclk emac1 reference clock g pg_06 eth1_rxd0 emac1 receive data 0 g pg_00 eth1_rxd1 emac1 receive data 1 e pe_15 eth1_txd0 emac1 transmit data 0 g pg_03 eth1_txd1 emac1 transmit data 1 g pg_02 eth1_txen emac1 transmit enable g pg_05 eth_ptpauxin emac0/emac1 ptp auxiliary trigger input c pc_11 table 7. adsp-bf60x 349-ball csp_bga signal descriptions (continued) signal name description port pin name
rev. 0 | page 25 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 eth_ptpclkin emac0/emac1 ptp clock input c pc_13 gnd ground not muxed gnd jtg_emu emulation output not muxed jtg_emu jtg_tck jtag clock not muxed jtg_tck jtg_tdi jtag serial data input not muxed jtg_tdi jtg_tdo jtag serial data output not muxed jtg_tdo jtg_tms jtag mode select not muxed jtg_tms jtg_trst jtag reset not muxed jtg_trst lp0_ack lp0 acknowledge b pb_01 lp0_clk lp0 clock b pb_00 lp0_d0 lp0 data 0 a pa_00 lp0_d1 lp0 data 1 a pa_01 lp0_d2 lp0 data 2 a pa_02 lp0_d3 lp0 data 3 a pa_03 lp0_d4 lp0 data 4 a pa_04 lp0_d5 lp0 data 5 a pa_05 lp0_d6 lp0 data 6 a pa_06 lp0_d7 lp0 data 7 a pa_07 lp1_ack lp1 acknowledge b pb_02 lp1_clk lp1 clock b pb_03 lp1_d0 lp1 data 0 a pa_08 lp1_d1 lp1 data 1 a pa_09 lp1_d2 lp1 data 2 a pa_10 lp1_d3 lp1 data 3 a pa_11 lp1_d4 lp1 data 4 a pa_12 lp1_d5 lp1 data 5 a pa_13 lp1_d6 lp1 data 6 a pa_14 lp1_d7 lp1 data 7 a pa_15 lp2_ack lp2 acknowledge e pe_08 lp2_clk lp2 clock e pe_09 lp2_d0 lp2 data 0 f pf_00 lp2_d1 lp2 data 1 f pf_01 lp2_d2 lp2 data 2 f pf_02 lp2_d3 lp2 data 3 f pf_03 lp2_d4 lp2 data 4 f pf_04 lp2_d5 lp2 data 5 f pf_05 lp2_d6 lp2 data 6 f pf_06 lp2_d7 lp2 data 7 f pf_07 lp3_ack lp3 acknowledge e pe_07 lp3_clk lp3 clock e pe_06 lp3_d0 lp3 data 0 f pf_08 lp3_d1 lp3 data 1 f pf_09 lp3_d2 lp3 data 2 f pf_10 lp3_d3 lp3 data 3 f pf_11 lp3_d4 lp3 data 4 f pf_12 lp3_d5 lp3 data 5 f pf_13 table 7. adsp-bf60x 349-ball csp_bga signal descriptions (continued) signal name description port pin name
rev. 0 | page 26 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 lp3_d6 lp3 data 6 f pf_14 lp3_d7 lp3 data 7 f pf_15 pa_00 C pa_15 porta position 00 through porta position 15 a pa_00 C pa_15 pb_00 C pb_15 portb position 00 through portb position 15 b pb_00 C pb_15 pc_00 C pc_15 portc position 00 through portc position 15 c pc_00 C pc_15 pd_00 C pd_15 portd position 00 through portd position 15 d pd_00 C pd_15 pe_00 C pe_15 porte position 00 thro ugh porte position 15 e pe_00 C pe_15 pf_00 C pf_15 portf position 00 thro ugh portf position 15 f pf_00 C pf_15 pg_00 C pg_15 portg position 00 through portg position 15 g pg_00 C pg_15 ppi0_clk eppi0 clock e pe_09 ppi0_d00 eppi0 data 0 f pf_00 ppi0_d01 eppi0 data 1 f pf_01 ppi0_d02 eppi0 data 2 f pf_02 ppi0_d03 eppi0 data 3 f pf_03 ppi0_d04 eppi0 data 4 f pf_04 ppi0_d05 eppi0 data 5 f pf_05 ppi0_d06 eppi0 data 6 f pf_06 ppi0_d07 eppi0 data 7 f pf_07 ppi0_d08 eppi0 data 8 f pf_08 ppi0_d09 eppi0 data 9 f pf_09 ppi0_d10 eppi0 data 10 f pf_10 ppi0_d11 eppi0 data 11 f pf_11 ppi0_d12 eppi0 data 12 f pf_12 ppi0_d13 eppi0 data 13 f pf_13 ppi0_d14 eppi0 data 14 f pf_14 ppi0_d15 eppi0 data 15 f pf_15 ppi0_d16 eppi0 data 16 e pe_03 ppi0_d17 eppi0 data 17 e pe_04 ppi0_d18 eppi0 data 18 e pe_00 ppi0_d19 eppi0 data 19 e pe_01 ppi0_d20 eppi0 data 20 d pd_12 ppi0_d21 eppi0 data 21 d pd_15 ppi0_d22 eppi0 data 22 e pe_02 ppi0_d23 eppi0 data 23 e pe_05 ppi0_fs1 eppi0 frame sync 1 (hsync) e pe_08 ppi0_fs2 eppi0 frame sync 2 (vsync) e pe_07 ppi0_fs3 eppi0 frame sync 3 (field) e pe_06 ppi1_clk eppi1 clock b pb_14 ppi1_d00 eppi1 data 0 c pc_00 ppi1_d01 eppi1 data 1 c pc_01 ppi1_d02 eppi1 data 2 c pc_02 ppi1_d03 eppi1 data 3 c pc_03 ppi1_d04 eppi1 data 4 c pc_04 ppi1_d05 eppi1 data 5 c pc_05 ppi1_d06 eppi1 data 6 c pc_06 ppi1_d07 eppi1 data 7 c pc_07 table 7. adsp-bf60x 349-ball csp_bga signal descriptions (continued) signal name description port pin name
rev. 0 | page 27 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 ppi1_d08 eppi1 data 8 c pc_08 ppi1_d09 eppi1 data 9 c pc_09 ppi1_d10 eppi1 data 10 c pc_10 ppi1_d11 eppi1 data 11 c pc_11 ppi1_d12 eppi1 data 12 c pc_12 ppi1_d13 eppi1 data 13 c pc_13 ppi1_d14 eppi1 data 14 c pc_14 ppi1_d15 eppi1 data 15 c pc_15 ppi1_d16 eppi1 data 16 d pd_00 ppi1_d17 eppi1 data 17 d pd_01 ppi1_fs1 eppi1 frame sync 1 (hsync) b pb_13 ppi1_fs2 eppi1 frame sync 2 (vsync) d pd_06 ppi1_fs3 eppi1 frame sync 3 (field) b pb_15 ppi2_clk eppi2 clock b pb_00 ppi2_d00 eppi2 data 0 a pa_00 ppi2_d01 eppi2 data 1 a pa_01 ppi2_d02 eppi2 data 2 a pa_02 ppi2_d03 eppi2 data 3 a pa_03 ppi2_d04 eppi2 data 4 a pa_04 ppi2_d05 eppi2 data 5 a pa_05 ppi2_d06 eppi2 data 6 a pa_06 ppi2_d07 eppi2 data 7 a pa_07 ppi2_d08 eppi2 data 8 a pa_08 ppi2_d09 eppi2 data 9 a pa_09 ppi2_d10 eppi2 data 10 a pa_10 ppi2_d11 eppi2 data 11 a pa_11 ppi2_d12 eppi2 data 12 a pa_12 ppi2_d13 eppi2 data 13 a pa_13 ppi2_d14 eppi2 data 14 a pa_14 ppi2_d15 eppi2 data 15 a pa_15 ppi2_d16 eppi2 data 16 b pb_07 ppi2_d17 eppi2 data 17 b pb_08 ppi2_fs1 eppi2 frame sync 1 (hsync) b pb_01 ppi2_fs2 eppi2 frame sync 2 (vsync) b pb_02 ppi2_fs3 eppi2 frame sync 3 (field) b pb_03 pwm0_ah pwm0 channel a high side f pf_01 pwm0_al pwm0 channel a low side f pf_00 pwm0_bh pwm0 channel b high side f pf_03 pwm0_bl pwm0 channel b low side f pf_02 pwm0_ch pwm0 channel c high side f pf_05 pwm0_cl pwm0 channel c low side f pf_04 pwm0_dh pwm0 channel d high side f pf_07 pwm0_dl pwm0 channel d low side f pf_06 pwm0_sync pwm0 sync e pe_08 pwm0_trip0 pwm0 shutdown input 0 e pe_09 pwm0_trip1 pwm0 shutdown input 1 f pf_11 table 7. adsp-bf60x 349-ball csp_bga signal descriptions (continued) signal name description port pin name
rev. 0 | page 28 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 pwm1_ah pwm1 channel a high side g pg_03 pwm1_al pwm1 channel a low side g pg_02 pwm1_bh pwm1 channel b high side g pg_00 pwm1_bl pwm1 channel b low side e pe_15 pwm1_ch pwm1 channel c high side e pe_13 pwm1_cl pwm1 channel c low side e pe_12 pwm1_dh pwm1 channel d high side e pe_11 pwm1_dl pwm1 channel d low side e pe_10 pwm1_sync pwm1 sync g pg_05 pwm1_trip0 pwm1 shutdown input 0 g pg_06 pwm1_trip1 pwm1 shutdown input 1 g pg_08 rsi0_clk rsi0 clock g pg_06 rsi0_cmd rsi0 command g pg_05 rsi0_d0 rsi0 data 0 g pg_03 rsi0_d1 rsi0 data 1 g pg_02 rsi0_d2 rsi0 data 2 g pg_00 rsi0_d3 rsi0 data 3 e pe_15 rsi0_d4 rsi0 data 4 e pe_13 rsi0_d5 rsi0 data 5 e pe_12 rsi0_d6 rsi0 data 6 e pe_10 rsi0_d7 rsi0 data 7 e pe_11 smc0_a01 smc0 address 1 not muxed smc0_a01 smc0_a02 smc0 address 2 not muxed smc0_a02 smc0_a03 smc0 address 3 a pa_00 smc0_a04 smc0 address 4 a pa_01 smc0_a05 smc0 address 5 a pa_02 smc0_a06 smc0 address 6 a pa_03 smc0_a07 smc0 address 7 a pa_04 smc0_a08 smc0 address 8 a pa_05 smc0_a09 smc0 address 9 a pa_06 smc0_a10 smc0 address 10 a pa_07 smc0_a11 smc0 address 11 a pa_08 smc0_a12 smc0 address 12 a pa_09 smc0_a13 smc0 address 13 b pb_02 smc0_a14 smc0 address 14 a pa_10 smc0_a15 smc0 address 15 a pa_11 smc0_a16 smc0 address 16 b pb_03 smc0_a17 smc0 address 17 a pa_12 smc0_a18 smc0 address 18 a pa_13 smc0_a19 smc0 address 19 a pa_14 smc0_a20 smc0 address 20 a pa_15 smc0_a21 smc0 address 21 b pb_06 smc0_a22 smc0 address 22 b pb_07 smc0_a23 smc0 address 23 b pb_08 smc0_a24 smc0 address 24 b pb_10 smc0_a25 smc0 address 25 b pb_11 table 7. adsp-bf60x 349-ball csp_bga signal descriptions (continued) signal name description port pin name
rev. 0 | page 29 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 smc0_abe0 smc0 byte enable 0 b pb_04 smc0_abe1 smc0 byte enable 1 b pb_05 smc0_ams0 smc0 memory select 0 not muxed smc0_ams0 smc0_ams1 smc0 memory select 1 b pb_01 smc0_ams2 smc0 memory select 2 b pb_04 smc0_ams3 smc0 memory select 3 b pb_05 smc0_aoe smc0 output enable not muxed smc0_aoe _nordv smc0_ardy smc0 asynchronous ready not muxed smc0_ardy_norwt smc0_are smc0 read enable not muxed smc0_are smc0_awe smc0 write enable not muxed smc0_awe smc0_bgh smc0 bus grant hang b pb_09 smc0_bg smc0 bus grant b pb_12 smc0_br smc0 bus request not muxed smc0_br smc0_d00 smc0 data 0 not muxed smc0_d00 smc0_d01 smc0 data 1 not muxed smc0_d01 smc0_d02 smc0 data 2 not muxed smc0_d02 smc0_d03 smc0 data 3 not muxed smc0_d03 smc0_d04 smc0 data 4 not muxed smc0_d04 smc0_d05 smc0 data 5 not muxed smc0_d05 smc0_d06 smc0 data 6 not muxed smc0_d06 smc0_d07 smc0 data 7 not muxed smc0_d07 smc0_d08 smc0 data 8 not muxed smc0_d08 smc0_d09 smc0 data 9 not muxed smc0_d09 smc0_d10 smc0 data 10 not muxed smc0_d10 smc0_d11 smc0 data 11 not muxed smc0_d11 smc0_d12 smc0 data 12 not muxed smc0_d12 smc0_d13 smc0 data 13 not muxed smc0_d13 smc0_d14 smc0 data 14 not muxed smc0_d14 smc0_d15 smc0 data 15 not muxed smc0_d15 smc0_norclk smc0 nor clock b pb_00 smc0_nordv smc0 nor data valid not muxed smc0_aoe _nordv smc0_norwt smc0 nor wait not muxed smc0_ardy_norwt spi0_clk spi0 clock d pd_04 spi0_d2 spi0 data 2 d pd_00 spi0_d3 spi0 data 3 d pd_01 spi0_miso spi0 master in, slave out d pd_02 spi0_mosi spi0 master out, slave in d pd_03 spi0_rdy spi0 ready d pd_10 spi0_sel1 spi0 slave select output 1 d pd_11 spi0_sel2 spi0 slave select output 2 d pd_01 spi0_sel3 spi0 slave select output 3 d pd_00 spi0_sel4 spi0 slave select output 4 c pc_15 spi0_sel5 spi0 slave select output 5 d pd_09 spi0_sel6 spi0 slave select output 6 c pc_13 spi0_sel7 spi0 slave select output 7 c pc_12 spi0_ss spi0 slave select input d pd_11 table 7. adsp-bf60x 349-ball csp_bga signal descriptions (continued) signal name description port pin name
rev. 0 | page 30 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 spi1_clk spi1 clock d pd_05 spi1_d2 spi1 data 2 e pe_01 spi1_d3 spi1 data 3 e pe_00 spi1_miso spi1 master in, slave out d pd_14 spi1_mosi spi1 master out, slave in d pd_13 spi1_rdy spi1 ready e pe_02 spi1_sel1 spi1 slave select output 1 d pd_12 spi1_sel2 spi1 slave select output 2 d pd_15 spi1_sel3 spi1 slave select output 3 d pd_10 spi1_sel4 spi1 slave select output 4 d pd_09 spi1_sel5 spi1 slave select output 5 f pf_08 spi1_sel6 spi1 slave select output 6 f pf_09 spi1_sel7 spi1 slave select output 7 c pc_14 spi1_ss spi1 slave select input d pd_12 spt0_aclk sport0 channel a clock b pb_05 spt0_ad0 sport0 channel a data 0 b pb_09 spt0_ad1 sport0 channel a data 1 b pb_12 spt0_afs sport0 channel a frame sync b pb_04 spt0_atdv sport0 channel a tr ansmit data valid b pb_06 spt0_bclk sport0 channel b clock b pb_08 spt0_bd0 sport0 channel b data 0 b pb_11 spt0_bd1 sport0 channel b data 1 b pb_10 spt0_bfs sport0 channel b frame sync b pb_07 spt0_btdv sport0 channel b transmit data valid b pb_12 spt1_aclk sport1 channel a clock e pe_02 spt1_ad0 sport1 channel a data 0 d pd_15 spt1_ad1 sport1 channel a data 1 d pd_12 spt1_afs sport1 channel a frame sync e pe_05 spt1_atdv sport1 channel a tr ansmit data valid e pe_06 spt1_bclk sport1 channel b clock e pe_04 spt1_bd0 sport1 channel b data 0 e pe_01 spt1_bd1 sport1 channel b data 1 e pe_00 spt1_bfs sport1 channel b frame sync e pe_03 spt1_btdv sport1 channel b transmit data valid e pe_07 spt2_aclk sport2 channel a clock g pg_04 spt2_ad0 sport2 channel a data 0 g pg_09 spt2_ad1 sport2 channel a data 1 g pg_08 spt2_afs sport2 channel a frame sync g pg_01 spt2_atdv sport2 channel a tr ansmit data valid e pe_14 spt2_bclk sport2 channel b clock g pg_10 spt2_bd0 sport2 channel b data 0 g pg_12 spt2_bd1 sport2 channel b data 1 g pg_11 spt2_bfs sport2 channel b frame sync g pg_07 spt2_btdv sport2 channel b transmit data valid g pg_06 sys_bmode0 boot mode control 0 not muxed sys_bmode0 sys_bmode1 boot mode control 1 not muxed sys_bmode1 table 7. adsp-bf60x 349-ball csp_bga signal descriptions (continued) signal name description port pin name
rev. 0 | page 31 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 sys_bmode2 boot mode control 2 not muxed sys_bmode2 sys_clkin clock/crystal input not muxed sys_clkin sys_clkout processor clock output not muxed sys_clkout sys_extwake external wake control not muxed sys_extwake sys_fault fault output not muxed sys_fault sys_fault complementary fault output not muxed sys_fault sys_hwrst processor hardware reset control not muxed sys_hwrst sys_idle0 core 0 idle indicator g pg_15 sys_idle1 core 1 idle indicator g pg_14 sys_nmi non-maskable interrupt not muxed sys_nmi_ reso u t sys_pwrgd power good indicator not muxed sys_pwrgd sys_resout reset output not muxed sys_nmi_ res o ut sys_sleep processor sleep indicator g pg_15 sys_tda thermal diode anode not muxed sys_tda sys_tdk thermal diode cathode not muxed sys_tdk sys_xtal crystal output not muxed sys_xtal tm0_aci0 timer0 alternate capture input 0 d pd_08 tm0_aci1 timer0 alternate capture input 1 g pg_14 tm0_aci2 timer0 alternate capture input 2 g pg_04 tm0_aci3 timer0 alternate capture input 3 d pd_07 tm0_aci4 timer0 alternate capture input 4 g pg_15 tm0_aci5 timer0 alternate capture input 5 d pd_06 tm0_aci6 timer0 alternate capture input 6 b pb_13 tm0_aclk0 timer0 alternate clock 0 b pb_10 tm0_aclk1 timer0 alternate clock 1 b pb_12 tm0_aclk2 timer0 alternate clock 2 b pb_09 tm0_aclk3 timer0 alternate clock 3 b pb_11 tm0_aclk4 timer0 alternate clock 4 b pb_06 tm0_aclk5 timer0 alternate clock 5 d pd_13 tm0_aclk6 timer0 alternate clock 6 d pd_14 tm0_aclk7 timer0 alternate clock 7 d pd_05 tm0_clk timer0 clock g pg_13 tm0_tmr0 timer0 timer 0 e pe_14 tm0_tmr1 timer0 timer 1 g pg_04 tm0_tmr2 timer0 timer 2 g pg_01 tm0_tmr3 timer0 timer 3 g pg_08 tm0_tmr4 timer0 timer 4 g pg_09 tm0_tmr5 timer0 timer 5 g pg_07 tm0_tmr6 timer0 timer 6 g pg_11 tm0_tmr7 timer0 timer 7 g pg_12 twi0_scl twi0 serial clock not muxed twi0_scl twi0_sda twi0 serial data not muxed twi0_sda twi1_scl twi1 serial clock not muxed twi1_scl twi1_sda twi1 serial data not muxed twi1_sda uart0_cts uart0 clear to send d pd_10 uart0_rts uart0 request to send d pd_09 table 7. adsp-bf60x 349-ball csp_bga signal descriptions (continued) signal name description port pin name
rev. 0 | page 32 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 uart0_rx uart0 receive d pd_08 uart0_tx uart0 transmit d pd_07 uart1_cts uart1 clear to send g pg_13 uart1_rts uart1 request to send g pg_10 uart1_rx uart1 receive g pg_14 uart1_tx uart1 transmit g pg_15 usb0_clkin usb0 clock/crysta l input not muxed usb0_clkin usb0_dm usb0 data C not muxed usb0_dm usb0_dp usb0 data + not muxed usb0_dp usb0_id usb0 otg id not muxed usb0_id usb0_vbc usb0 vbus cont rol not muxed usb0_vbc usb0_vbus usb0 bus voltage not muxed usb0_vbus vdd_dmc vdd for dmc not muxed vdd_dmc vdd_ext external vdd not muxed vdd_ext vdd_int internal vdd not muxed vdd_int vdd_td vdd for thermal diode not muxed vdd_td vdd_usb vdd for usb not muxed vdd_usb vref_dmc vref for dmc not muxed vref_dmc table 7. adsp-bf60x 349-ball csp_bga signal descriptions (continued) signal name description port pin name
rev. 0 | page 33 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 gp i/o multiplexing for 349-ball csp_bga table 8 through table 14 identifies the pin functions that are multiplexed on the general-pu rpose i/o pins of the 349-ball csp_bga package. table 8. signal multiplexing for port a signal name multiplexed function 0 multiplexed function 1 multiplexed function 2 multiplexed function input tap pa_00 smc0_a03 ppi2_d00 lp0_d0 pa_01 smc0_a04 ppi2_d01 lp0_d1 pa_02 smc0_a05 ppi2_d02 lp0_d2 pa_03 smc0_a06 ppi2_d03 lp0_d3 pa_04 smc0_a07 ppi2_d04 lp0_d4 pa_05 smc0_a08 ppi2_d05 lp0_d5 pa_06 smc0_a09 ppi2_d06 lp0_d6 pa_07 smc0_a10 ppi2_d07 lp0_d7 pa_08 smc0_a11 ppi2_d08 lp1_d0 pa_09 smc0_a12 ppi2_d09 lp1_d1 pa_10 smc0_a14 ppi2_d10 lp1_d2 pa_11 smc0_a15 ppi2_d11 lp1_d3 pa_12 smc0_a17 ppi2_d12 lp1_d4 pa_13 smc0_a18 ppi2_d13 lp1_d5 pa_14 smc0_a19 ppi2_d14 lp1_d6 pa_15 smc0_a20 ppi2_d15 lp1_d7 table 9. signal multiplexing for port b signal name multiplexed function 0 multiplexed function 1 multiplexed function 2 multiplexed function input tap pb_00 smc0_norclk ppi2_clk lp0_clk pb_01 smc0_ams1 ppi2_fs1 lp0_ack pb_02 smc0_a13 ppi2_fs2 lp1_ack pb_03 smc0_a16 ppi2_fs3 lp1_clk pb_04 smc0_ams2 smc0_abe0 spt0_afs pb_05 smc0_ams3 smc0_abe1 spt0_aclk pb_06 smc0_a21 spt0_atdv tm0_aclk4 pb_07 smc0_a22 ppi2_d16 spt0_bfs pb_08 smc0_a23 ppi2_d17 spt0_bclk pb_09 smc0_bgh spt0_ad0 tm0_aclk2 pb_10 smc0_a24 spt0_bd1 tm0_aclk0 pb_11 smc0_a25 spt0_bd0 tm0_aclk3 pb_12 smc0_bg spt0_btdv spt0_ad1 tm0_aclk1 pb_13 eth0_txen ppi1_fs1 tm0_aci6 pb_14 eth0_refclk ppi1_clk pb_15 eth0_ptppps ppi1_fs3
rev. 0 | page 34 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 table 10. signal multiplexing for port c signal name multiplexed function 0 multiplexed function 1 multiplexed function 2 multiplexed function input tap pc_00 eth0_rxd0 ppi1_d00 pc_01 eth0_rxd1 ppi1_d01 pc_02 eth0_txd0 ppi1_d02 pc_03 eth0_txd1 ppi1_d03 pc_04 ppi1_d04 pc_05 eth0_crs ppi1_d05 pc_06 eth0_mdc ppi1_d06 pc_07 eth0_mdio ppi1_d07 pc_08 ppi1_d08 pc_09 eth1_ptppps ppi1_d09 pc_10 ppi1_d10 pc_11 ppi1_d11 eth_ptpauxin pc_12 spi0_sel7 ppi1_d12 pc_13 spi0_sel6 ppi1_d13 eth_ptpclkin pc_14 spi1_sel7 ppi1_d14 pc_15 spi0_sel4 ppi1_d15 table 11. signal multiplexing for port d signal name multiplexed function 0 multiplexed function 1 multiplexed function 2 multiplexed function input tap pd_00 spi0_d2 ppi1_d16 spi0_sel3 pd_01 spi0_d3 ppi1_d17 spi0_sel2 pd_02 spi0_miso pd_03 spi0_mosi pd_04 spi0_clk pd_05 spi1_clk tm0_aclk7 pd_06 ppi1_fs2 tm0_aci5 pd_07 uart0_tx tm0_aci3 pd_08 uart0_rx tm0_aci0 pd_09 spi0_sel5 uart0_rts spi1_sel4 pd_10 spi0_rdy uart0_cts spi1_sel3 pd_11 spi0_sel1 spi0_ss pd_12 spi1_sel1 ppi0_d20 spt1_ad1 spi1_ss pd_13 spi1_mosi tm0_aclk5 pd_14 spi1_miso tm0_aclk6 pd_15 spi1_sel2 ppi0_d21 spt1_ad0
rev. 0 | page 35 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 table 12. signal multiplexing for port e signal name multiplexed function 0 multiplexed function 1 multiplexed function 2 multiplexed function input tap pe_00 spi1_d3 ppi0_d18 spt1_bd1 pe_01 spi1_d2 ppi0_d19 spt1_bd0 pe_02 spi1_rdy ppi0_d22 spt1_aclk pe_03 ppi0_d16 acm0_fs/spt1_bfs pe_04 ppi0_d17 acm0_clk/spt1_bclk pe_05 ppi0_d23 spt1_afs pe_06 spt1_atdv ppi0_fs3 lp3_clk pe_07 spt1_btdv ppi0_fs2 lp3_ack pe_08 pwm0_sync ppi0_fs1 lp2_ack acm0_t0 pe_09 ppi0_clk lp2_clk pwm0_trip0 pe_10 eth1_mdc pwm1_dl rsi0_d6 pe_11 eth1_mdio pwm1_dh rsi0_d7 pe_12 pwm1_cl rsi0_d5 pe_13 eth1_crs pwm1_ch rsi0_d4 pe_14 spt2_atdv tm0_tmr0 pe_15 eth1_rxd1 pwm1_bl rsi0_d3 table 13. signal multiplexing for port f signal name multiplexed function 0 multiplexed function 1 multiplexed function 2 multiplexed function input tap pf_00 pwm0_al ppi0_d00 lp2_d0 pf_01 pwm0_ah ppi0_d01 lp2_d1 pf_02 pwm0_bl ppi0_d02 lp2_d2 pf_03 pwm0_bh ppi0_d03 lp2_d3 pf_04 pwm0_cl ppi0_d04 lp2_d4 pf_05 pwm0_ch ppi0_d05 lp2_d5 pf_06 pwm0_dl ppi0_d06 lp2_d6 pf_07 pwm0_dh ppi0_d07 lp2_d7 pf_08 spi1_sel5 ppi0_d08 lp3_d0 pf_09 spi1_sel6 ppi0_d09 lp3_d1 pf_10 acm0_a4 ppi0_d10 lp3_d2 pf_11 ppi0_d11 lp3_d3 pwm0_trip1 pf_12 acm0_a2 ppi0_d12 lp3_d4 pf_13 acm0_a3 ppi0_d13 lp3_d5 pf_14 acm0_a0 ppi0_d14 lp3_d6 pf_15 acm0_a1 ppi0_d15 lp3_d7
rev. 0 | page 36 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 table 14. signal multiplexing for port g signal name multiplexed function 0 multiplexed function 1 multiplexed function 2 multiplexed function input tap pg_00 eth1_rxd0 pwm1_bh rsi0_d2 pg_01 spt2_afs tm0_tmr2 can0_tx pg_02 eth1_txd1 pwm1_al rsi0_d1 pg_03 eth1_txd0 pwm1_ah rsi0_d0 pg_04 spt2_aclk tm0_tmr1 can0_rx tm0_aci2 pg_05 eth1_txen rsi0_cmd pwm1_sync acm0_t1 pg_06 eth1_refclk rsi0_c lk spt2_btdv pwm1_trip0 pg_07 spt2_bfs tm0_tmr5 cnt0_zm pg_08 spt2_ad1 tm0_tmr3 pwm1_trip1 pg_09 spt2_ad0 tm0_tmr4 pg_10 uart1_rts spt2_bclk pg_11 spt2_bd1 tm0_tmr6 cnt0_ud pg_12 spt2_bd0 tm0_tmr7 cnt0_dg pg_13 uart1_cts tm0_clk pg_14 uart1_rx sys_idle1 tm0_aci1 pg_15 uart1_tx sys_idle0 sys_sleep tm0_aci4
rev. 0 | page 37 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 adsp-bf60x designer quick reference the table provides a quick refe rence summary of pin related information for circuit board desi gn. the columns in this table provide the following information: ? signal name: the signal name column in the table includes the signal name for every pin. ? type: the pin type column in the table identifies the i/o type or supply type of the pi n. the abbreviations used in this column are na (none), i/o (digital input and/or out- put), a (analog), s (supply), and g (ground). ? driver type: the driver type column in the table identi- fies the driver type used by the pin. the driver types are defined in output drive currents on page 99 . ? int term: the internal termination column in the table specifies the termination present when the processor is not in the reset or hibernate stat e. the abbreviations used in this column are wk (weak keep er, weakly retains previous value driven on the pin), pu (pull-up resistor), or pd (pull- down resistor). ? reset term: the reset termination column in the table specifies the termination presen t when the processor is in the reset state. the abbreviations used in this column are wk (weak keeper, weak ly retains previous value driven on the pin), pu (pull-up resistor), or pd (pull-down resistor). ? reset drive: the reset drive column in the table specifies the active drive on the signal when the processor is in the reset state. ? hiber term: the hibernate termination column in the table specifies the terminatio n present when the processor is in the hibernate state. the abbreviations used in this col- umn are wk (weak keeper, weak ly retains previous value driven on the pin), pu (pull-up resistor), or pd (pull-down resistor). ? hiber drive: the hibernate drive column in the table specifies the active drive on th e signal when the processor is in the hibernate state. ? power domain: the power do main column in the table specifies the power supply domain in which the signal resides. ? description and notes: the description and notes column in the table identifies any sp ecial requirements or charac- teristics for the signal. if no special requirements are listed the signal may be left unconnected if it is not used. also, for multiplexed general-purpose i/ o pins, this column identi- fies the functions available on the pin. table 15. adsp-bf60x designer quick reference signal name type driver type int term reset term reset drive hiber term hiber drive power domain description and notes dmc0_a00 i/o b none none none none none vdd_dmc desc: dmc0 address 0. notes: no notes. dmc0_a01 i/o b none none none none none vdd_dmc desc: dmc0 address 1. notes: no notes. dmc0_a02 i/o b none none none none none vdd_dmc desc: dmc0 address 2. notes: no notes. dmc0_a03 i/o b none none none none none vdd_dmc desc: dmc0 address 3. notes: no notes. dmc0_a04 i/o b none none none none none vdd_dmc desc: dmc0 address 4. notes: no notes. dmc0_a05 i/o b none none none none none vdd_dmc desc: dmc0 address 5. notes: no notes. dmc0_a06 i/o b none none none none none vdd_dmc desc: dmc0 address 6. notes: no notes. dmc0_a07 i/o b none none none none none vdd_dmc desc: dmc0 address 7. notes: no notes. dmc0_a08 i/o b none none none none none vdd_dmc desc: dmc0 address 8. notes: no notes. dmc0_a09 i/o b none none none none none vdd_dmc desc: dmc0 address 9. notes: no notes. dmc0_a10 i/o b none none none none none vdd_dmc desc: dmc0 address 10. notes: no notes.
rev. 0 | page 38 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 dmc0_a11 i/o b none none none none none vdd_dmc desc: dmc0 address 11. notes: no notes. dmc0_a12 i/o b none none none none none vdd_dmc desc: dmc0 address 12. notes: no notes. dmc0_a13 i/o b none none none none none vdd_dmc desc: dmc0 address 13. notes: no notes. dmc0_ba0 i/o b none none none none none vdd_dmc desc: dmc0 bank address input 0. notes: no notes. dmc0_ba1 i/o b none none none none none vdd_dmc desc: dmc0 bank address input 1. notes: no notes. dmc0_ba2 i/o b none none none none none vdd_dmc desc: dmc0 bank address input 2. notes: for lpddr, leave unconnected. dmc0_cas i/o b none none none none none vdd_dmc desc: dmc0 column address strobe. notes: no notes. dmc0_ck i/o c none none l none l vdd_dmc desc: dmc0 clock. notes: no notes. dmc0_ck i/o c none none l none l vdd_dmc desc: dmc0 clock (complement). notes: no notes. dmc0_cke i/o b none none l none l vdd_dmc desc: dmc0 clock enable. notes: no notes. dmc0_cs0 i/o b none none none none none vdd_dmc desc: dmc0 chip select 0. notes: no notes. dmc0_dq00 i/o b none none none none n one vdd_dmc desc: dmc0 data 0. notes: no notes. dmc0_dq01 i/o b none none none none n one vdd_dmc desc: dmc0 data 1. notes: no notes. dmc0_dq02 i/o b none none none none n one vdd_dmc desc: dmc0 data 2. notes: no notes. dmc0_dq03 i/o b none none none none n one vdd_dmc desc: dmc0 data 3. notes: no notes. dmc0_dq04 i/o b none none none none n one vdd_dmc desc: dmc0 data 4. notes: no notes. dmc0_dq05 i/o b none none none none n one vdd_dmc desc: dmc0 data 5. notes: no notes. dmc0_dq06 i/o b none none none none n one vdd_dmc desc: dmc0 data 6. notes: no notes. dmc0_dq07 i/o b none none none none n one vdd_dmc desc: dmc0 data 7. notes: no notes. dmc0_dq08 i/o b none none none none n one vdd_dmc desc: dmc0 data 8. notes: no notes. dmc0_dq09 i/o b none none none none n one vdd_dmc desc: dmc0 data 9. notes: no notes. dmc0_dq10 i/o b none none none none non e vdd_dmc desc: dmc0 data 10. notes: no notes. dmc0_dq11 i/o b none none none none non e vdd_dmc desc: dmc0 data 11. notes: no notes. dmc0_dq12 i/o b none none none none non e vdd_dmc desc: dmc0 data 12. notes: no notes. table 15. adsp-bf60x designer quick reference (continued) signal name type driver type int term reset term reset drive hiber term hiber drive power domain description and notes
rev. 0 | page 39 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 dmc0_dq13 i/o b none none none none non e vdd_dmc desc: dmc0 data 13. notes: no notes. dmc0_dq14 i/o b none none none none non e vdd_dmc desc: dmc0 data 14. notes: no notes. dmc0_dq15 i/o b none none none none non e vdd_dmc desc: dmc0 data 15. notes: no notes. dmc0_ldm i/o b none none none none none vdd_dmc desc: dmc0 data mask for lower byte. notes: no notes. dmc0_ldqs i/o c none none none none none vdd_dmc de sc: dmc0 data strobe for lower byte. notes: for lpddr, a 100k ohm pull-down resistor is required. dmc0_ldqs i/o c none none none none none vdd_dmc desc: dmc0 data strobe for lower byte (complement). notes: for single ended ddr2, connect to vref_dmc. for lpddr, leave unconnected. dmc0_odt i/o b none none none none none vdd_dmc desc: dmc0 on-die termination. notes: for lpddr, leave unconnected. dmc0_ras i/o b none none none none none vdd_dmc desc: dmc0 row address strobe. notes: no notes. dmc0_udm i/o b none none none none none vdd_dmc d esc: dmc0 data mask for upper byte. notes: no notes. dmc0_udqs i/o c none none none none none vdd_dmc de sc: dmc0 data strobe for upper byte. notes: for lpddr, a 100k ohm pull-down resistor is required. dmc0_udqs i/o c none none none none none vdd_dmc desc: dmc0 data strobe for upper byte (complement). notes: for single ended ddr2, connect to vref_dmc. for lpddr, leave unconnected. dmc0_we i/o b none none none none none vdd_dmc desc: dmc0 write enable. notes: no notes. gnd g na none none none none none na desc: ground. notes: no notes. jtg_emu i/o a none none none none none vdd_ext desc: emulation output. notes: no notes. jtg_tck i/o na pd none none none none vdd_ext desc: jtg clock. notes: functional during reset. jtg_tdi i/o na pu none none none none vdd_ext desc: jtg serial data input. notes: functional during reset. jtg_tdo i/o a none none none none none vdd_ext desc: jtg serial data output. notes: functional during reset, three- state when jtg_trst is asserted. jtg_tms i/o na pu none none none none vdd_ext desc: jtg mode select. notes: functional during reset. jtg_trst i/o na pd none none none none vdd_ext desc: jtg reset. notes: functional during reset. table 15. adsp-bf60x designer quick reference (continued) signal name type driver type int term reset term reset drive hiber term hiber drive power domain description and notes
rev. 0 | page 40 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 pa_00 i/o a wk wk none wk none vdd_ext desc: pa position 0 | smc0 address 3 | eppi2 data 0 | lp0 data 0. notes: no notes. pa_01 i/o a wk wk none wk none vdd_ext desc: pa position 1 | smc0 address 4 | eppi2 data 1 | lp0 data 1. notes: no notes. pa_02 i/o a wk wk none wk none vdd_ext desc: pa position 2 | smc0 address 5 | eppi2 data 2 | lp0 data 2. notes: no notes. pa_03 i/o a wk wk none wk none vdd_ext desc: pa position 3 | smc0 address 6 | eppi2 data 3 | lp0 data 3. notes: no notes. pa_04 i/o a wk wk none wk none vdd_ext desc: pa position 4 | smc0 address 7 | eppi2 data 4 | lp0 data 4. notes: no notes. pa_05 i/o a wk wk none wk none vdd_ext desc: pa position 5 | smc0 address 8 | eppi2 data 5 | lp0 data 5. notes: no notes. pa_06 i/o a wk wk none wk none vdd_ext desc: pa position 6 | smc0 address 9 | eppi2 data 6 | lp0 data 6. notes: no notes. pa_07 i/o a wk wk none wk none vdd_ext desc: pa position 7 | smc0 address 10 | eppi2 data 7 | lp0 data 7. notes: no notes. pa_08 i/o a wk wk none wk none vdd_ext desc: pa position 8 | smc0 address 11 | eppi2 data 8 | lp1 data 0. notes: no notes. pa_09 i/o a wk wk none wk none vdd_ext desc: pa position 9 | smc0 address 12 | eppi2 data 9 | lp1 data 1. notes: no notes. pa_10 i/o a wk wk none wk none vdd_ext desc: pa position 10 | smc0 address 14 | eppi2 data 10 | lp1 data 2. notes: no notes. pa_11 i/o a wk wk none wk none vdd_ext desc: pa position 11 | smc0 address 15 | eppi2 data 11 | lp1 data 3. notes: no notes. pa_12 i/o a wk wk none wk none vdd_ext desc: pa position 12 | smc0 address 17 | eppi2 data 12 | lp1 data 4. notes: no notes. pa_13 i/o a wk wk none wk none vdd_ext desc: pa position 13 | smc0 address 18 | eppi2 data 13 | lp1 data 5. notes: no notes. pa_14 i/o a wk wk none wk none vdd_ext desc: pa position 14 | smc0 address 19 | eppi2 data 14 | lp1 data 6. notes: no notes. pa_15 i/o a wk wk none wk none vdd_ext desc: pa position 15 | smc0 address 20 | eppi2 data 15 | lp1 data 7. notes: may be used to wake the processor from hibernate or deep sleep mode. table 15. adsp-bf60x designer quick reference (continued) signal name type driver type int term reset term reset drive hiber term hiber drive power domain description and notes
rev. 0 | page 41 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 pb_00 i/o a wk wk none wk none vdd_ext desc: pb position 0 | smc0 nor clock | eppi2 clock | lp0 clock. notes: no notes. pb_01 i/oa wkwknonewknonevdd_extdesc: pb position 1 | smc0 memory select 1 | eppi2 frame sync 1 (hsync) | lp0 acknowledge. notes: no notes. pb_02 i/oa wkwknonewknonevdd_extdesc: pb position 2 | smc0 address 13 | eppi2 frame sync 2 (vsync) | lp1 acknowledge. notes: no notes. pb_03 i/oa wkwknonewknonevdd_extdesc: pb position 3 | smc0 address 16 | eppi2 frame sync 3 (field) | lp1 clock. notes: no notes. pb_04 i/oa wkwknonewknonevdd_extdesc: pb position 4 | smc0 memory select 2 | smc0 byte enable 0 | sport0 channel a frame sync. notes: no notes. pb_05 i/oa wkwknonewknonevdd_extdesc: pb position 5 | smc0 memory select 3 | smc0 byte enable 1 | sport0 channel a clock. notes: no notes. pb_06 i/oa wkwknonewknonevdd_extdesc: pb position 6 | smc0 address 21 | sport0 channel a transmit data valid | timer0 alternate clock 4. notes: no notes. pb_07 i/oa wkwknonewknonevdd_extdesc: pb position 7 | smc0 address 22 | eppi2 data 16 | sport0 channel b frame sync. notes: no notes. pb_08 i/oa wkwknonewknonevdd_extdesc: pb position 8 | smc0 address 23 | eppi2 data 17 | sport0 channel b clock. notes: no notes. pb_09 i/oa wkwknonewknonevdd_extdesc: pb position 9 | smc0 bus grant hang | sport0 channel a data 0 | timer0 alternate clock 2. notes: no notes. pb_10 i/o a wk wk none wk none vdd_ext desc: pb position 10 | smc0 address 24 | sport0 channel b data 1 | timer0 alternate clock 0. notes: no notes. pb_11 i/o a wk wk none wk none vdd_ext desc: pb position 11 | smc0 address 25 | sport0 channel b data 0 | timer0 alternate clock 3. notes: no notes. pb_12 i/oa wkwknonewknonevdd_extdesc: pb position 12 | smc0 bus grant | sport0 channel b transmit data valid | sport0 channel a data 1 | timer0 alternate clock 1. notes: no notes. table 15. adsp-bf60x designer quick reference (continued) signal name type driver type int term reset term reset drive hiber term hiber drive power domain description and notes
rev. 0 | page 42 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 pb_13 i/oa wkwknonewknonevdd_extdesc: pb position 13 | eppi1 frame sync 1 (hsync) | eth0 transmit enable | timer0 alternate capture input 6. notes: no notes. pb_14 i/oa wkwknonewknonevdd_extdesc: pb position 14 | eppi1 clock | eth0 reference clock. notes: no notes. pb_15 i/oa wkwknonewknonevdd_extdesc: pb position 15 | eppi1 frame sync 3 (field) | eth0 ptp pulse-per-second output. notes: may be used to wake the processor from hibernate or deep sleep mode. pc_00 i/oa wkwknonewknonevdd_extdesc: pc position 0 | eppi1 data 0 | eth0 receive data 0. notes: no notes. pc_01 i/oa wkwknonewknonevdd_extdesc: pc position 1 | eppi1 data 1 | eth0 receive data 1. notes: no notes. pc_02 i/oa wkwknonewknonevdd_extdesc: pc position 2 | eppi1 data 2 | eth0 transmit data 0. notes: no notes. pc_03 i/oa wkwknonewknonevdd_extdesc: pc position 3 | eppi1 data 3 | eth0 transmit data 1. notes: no notes. pc_04 i/oa wkwknonewknonevdd_extdesc: pc position 4 | eppi1 data 4 | eth0 receive error. notes: no notes. pc_05 i/oa wkwknonewknonevdd_extdesc: pc position 5 | eppi1 data 5 | eth0 carrier sense/rmii receive data valid. notes: no notes. pc_06 i/oa wkwknonewknonevdd_extdesc: pc position 6 | eppi1 data 6 | eth0 management channel clock. notes: no notes. pc_07 i/oa wkwknonewknonevdd_extdesc: pc position 7 | eppi1 data 7 | eth0 management channel serial data. notes: no notes. pc_08 i/oa wkwknonewknonevdd_extdesc: pc position 8 | eppi1 data 8. notes: no notes. pc_09 i/oa wkwknonewknonevdd_extdesc: pc position 9 | eppi1 data 9 | eth1 ptp pulse-per-second output. notes: no notes. pc_10 i/oa wkwknonewknonevdd_extdesc: pc position 10 | eppi1 data 10. notes: no notes. pc_11 i/o a wk wk none wk none vdd_ext desc: pc position 11 | eppi1 data 11 | eth ptp auxiliary trigger input. notes: no notes. pc_12 i/oa wkwknonewknonevdd_extdesc: pc position 12 | spi0 slave select output b | eppi1 data 12. notes: no notes. table 15. adsp-bf60x designer quick reference (continued) signal name type driver type int term reset term reset drive hiber term hiber drive power domain description and notes
rev. 0 | page 43 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 pc_13 i/oa wkwknonewknonevdd_extdesc: pc position 13 | spi0 slave select output b | eppi1 data 13 | eth ptp clock input. notes: no notes. pc_14 i/oa wkwknonewknonevdd_extdesc: pc position 14 | spi1 slave select output b | eppi1 data 14. notes: no notes. pc_15 i/oa wkwknonewknonevdd_extdesc: pc position 15 | spi0 slave select output b | eppi1 data 15. notes: may be used to wake the processor from hibernate or deep sleep mode. pd_00 i/oa wkwknonewknonevdd_extdesc: pd position 0 | spi0 data 2 | eppi1 data 16 | spi0 slave select output b. notes: no notes. pd_01 i/oa wkwknonewknonevdd_extdesc: pd position 1 | spi0 data 3 | eppi1 data 17 | spi0 slave select output b. notes: no notes. pd_02 i/oa wkwknonewknonevdd_extdesc: pd position 2 | spi0 master in, slave out. notes: no notes. pd_03 i/oa wkwknonewknonevdd_extdesc: pd position 3 | spi0 master out, slave in. notes: no notes. pd_04 i/oa wkwknonewknonevdd_extdesc : pd position 4 | spi0 clock. notes: no notes. pd_05 i/oa wkwknonewknonevdd_extdesc: pd position 5 | spi1 clock | timer0 alternate clock 7. notes: no notes. pd_06 i/oa wkwknonewknonevdd_extdesc: pd position 6 | eppi1 frame sync 2 (vsync) | eth0 rmii management data interrupt | timer0 alternate capture input 5. notes: may be used to wake the processor from hibernate or deep sleep mode. pd_07 i/oa wkwknonewknonevdd_extdesc: pd position 7 | uart0 transmit | timer0 alternate capture input 3. notes: no notes. pd_08 i/oa wkwknonewknonevdd_extdesc: pd position 8 | uart0 receive | timer0 alternate capture input 0. notes: no notes. pd_09 i/o a wk wk none wk none vdd_ext desc: pd position 9 | spi1 slave select output b | uart0 request to send | spi0 slave select output b. notes: no notes. pd_10 i/oa wkwknonewknonevdd_extdesc: pd position 10 | spi0 ready | uart0 clear to send | spi1 slave select output b. notes: no notes. pd_11 i/oa wkwknonewknonevdd_extdesc: pd position 11 | spi0 slave select output b | spi0 slave select input. notes: no notes. table 15. adsp-bf60x designer quick reference (continued) signal name type driver type int term reset term reset drive hiber term hiber drive power domain description and notes
rev. 0 | page 44 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 pd_12 i/oa wkwknonewknonevdd_extdesc: pd position 12 | spi1 slave select output b | eppi0 data 20 | sport1 channel a data 1 | spi1 slave select input. notes: no notes. pd_13 i/o a wk wk none wk none vdd_ext desc: pd position 13 | spi1 master out, slave in | timer0 alternate clock 5. notes: no notes. pd_14 i/oa wkwknonewknonevdd_extdesc: pd position 14 | spi1 master in, slave out | timer0 alternate clock 6. notes: no notes. pd_15 i/oa wkwknonewknonevdd_extdesc: pd position 15 | spi1 slave select output b | eppi0 data 21 | sport1 channel a data 0. notes: no notes. pe_00 i/oa wkwknonewknonevdd_extdesc: pe position 0 | spi1 data 3 | eppi0 data 18 | sport1 channel b data 1. notes: no notes. pe_01 i/oa wkwknonewknonevdd_extdesc: pe position 1 | spi1 data 2 | eppi0 data 19 | sport1 channel b data 0. notes: no notes. pe_02 i/oa wkwknonewknonevdd_extdesc: pe position 2 | spi1 ready | eppi0 data 22 | sport1 channel a clock. notes: no notes. pe_03 i/oa wkwknonewknonevdd_extdesc: pe position 3 | eppi0 data 16 | sport1 channel b frame sync | acm0 frame sync. notes: no notes. pe_04 i/oa wkwknonewknonevdd_extdesc: pe position 4 | eppi0 data 17 | sport1 channel b clock | acm0 clock. notes: no notes. pe_05 i/oa wkwknonewknonevdd_extdesc: pe position 5 | eppi0 data 23 | sport1 channel a frame sync. notes: no notes. pe_06 i/o a wk wk none wk none vdd_ext desc: pe position 6 | sport1 channel a transmit data valid | eppi0 frame sync 3 (field) | lp3 clock. notes: no notes. pe_07 i/o a wk wk none wk none vdd_ext desc: pe position 7 | sport1 channel b transmit data valid | eppi0 frame sync 2 (vsync) | lp3 acknowledge. notes: no notes. pe_08 i/oa wkwknonewknonevdd_extdesc: pe position 8 | pwm0 sync | eppi0 frame sync 1 (hsync) | lp2 acknowledge | acm0 external trigger 0. notes: no notes. pe_09 i/oa wkwknonewknonevdd_extdesc: pe position 9 | eppi0 clock | lp2 clock | pwm0 shutdown input. notes: no notes. table 15. adsp-bf60x designer quick reference (continued) signal name type driver type int term reset term reset drive hiber term hiber drive power domain description and notes
rev. 0 | page 45 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 pe_10 i/oa wkwknonewknonevdd_extdesc: pe position 10 | pwm1 channel d low side | rsi0 data 6 | eth1 management channel clock. notes: has an optional internal pull-up resistor for use with rsi. see the rsi chapter in the processor hardware reference for more details. pe_11 i/oa wkwknonewknonevdd_extdesc: pe position 11 | pwm1 channel d high side | eth1 management channel serial data | rsi0 data 7. notes: has an optional internal pull-up resistor for use with rsi. see the rsi chapter in the processor hardware reference for more details. pe_12 i/oa wkwknonewknonevdd_extdesc: pe position 12 | pwm1 channel c low side | rsi0 data 5 | eth1 rmii management data interrupt. notes: has an optional internal pull-up resistor for use with rsi. see the rsi chapter in the processor hardware reference for more details. may be used to wake the processor from hibernate or deep sleep mode. pe_13 i/oa wkwknonewknonevdd_extdesc: pe position 13 | pwm1 channel c high side | rsi0 data 4 | eth1 carrier sense/rmii receive data valid. notes: has an optional internal pull-up resistor for use with rsi. see the rsi chapter in the processor hardware reference for more details. pe_14 i/oa wkwknonewknonevdd_extdesc: pe position 14 | sport2 channel a transmit data valid | timer0 timer 0 | eth1 receive error. notes: no notes. pe_15 i/oa wkwknonewknonevdd_extdesc: pe position 15 | pwm1 channel b low side | rsi0 data 3 | eth1 receive data 1. notes: has an optional internal pull-up resistor for use with rsi. see the rsi chapter in the processor hardware reference for more details. pf_00 i/o a wk wk none wk none vdd_ext desc: pf position 0 | pwm0 channel a low side | eppi0 data 0 | lp2 data 0. notes: no notes. pf_01 i/oa wkwknonewknonevdd_extdesc: pf position 1 | pwm0 channel a high side | eppi0 data 1 | lp2 data 1. notes: no notes. pf_02 i/o a wk wk none wk none vdd_ext desc: pf position 2 | pwm0 channel b low side | eppi0 data 2 | lp2 data 2. notes: no notes. table 15. adsp-bf60x designer quick reference (continued) signal name type driver type int term reset term reset drive hiber term hiber drive power domain description and notes
rev. 0 | page 46 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 pf_03 i/oa wkwknonewknonevdd_extdesc: pf position 3 | pwm0 channel b high side | eppi0 data 3 | lp2 data 3. notes: no notes. pf_04 i/o a wk wk none wk none vdd_ext desc: pf position 4 | pwm0 channel c low side | eppi0 data 4 | lp2 data 4. notes: no notes. pf_05 i/oa wkwknonewknonevdd_extdesc: pf position 5 | pwm0 channel c high side | eppi0 data 5 | lp2 data 5. notes: no notes. pf_06 i/oa wkwknonewknonevdd_extdesc: pf position 6 | pwm0 channel d low side | eppi0 data 6 | lp2 data 6. notes: no notes. pf_07 i/oa wkwknonewknonevdd_extdesc: pf position 7 | pwm0 channel d high side | eppi0 data 7 | lp2 data 7. notes: no notes. pf_08 i/o a wk wk none wk none vdd_ext desc: pf position 8 | spi1 slave select output b | eppi0 data 8 | lp3 data 0. notes: no notes. pf_09 i/o a wk wk none wk none vdd_ext desc: pf position 9 | spi1 slave select output b | eppi0 data 9 | lp3 data 1. notes: no notes. pf_10 i/oa wkwknonewknonevdd_extdesc: pf position 10 | acm0 address 4 | eppi0 data 10 | lp3 data 2. notes: no notes. pf_11 i/o a wk wk none wk none vdd_ext desc: pf position 11 | eppi0 data 11 | lp3 data 3 | pwm0 shutdown input. notes: no notes. pf_12 i/oa wkwknonewknonevdd_extdesc: pf position 12 | acm0 address 2 | eppi0 data 12 | lp3 data 4. notes: no notes. pf_13 i/oa wkwknonewknonevdd_extdesc: pf position 13 | acm0 address 3 | eppi0 data 13 | lp3 data 5. notes: no notes. pf_14 i/oa wkwknonewknonevdd_extdesc: pf position 14 | eppi0 data 14 | acm0 address 0 | lp3 data 6. notes: no notes. pf_15 i/oa wkwknonewknonevdd_extdesc: pf position 15 | acm0 address 1 | eppi0 data 15 | lp3 data 7. notes: no notes. pg_00 i/oa wkwknonewknonevdd_extdesc: pg position 0 | pwm1 channel b high side | rsi0 data 2 | eth1 receive data 0. notes: has an optional internal pull-up resistor for use with rsi. see the rsi chapter in the processor hardware reference for more details. pg_01 i/oa wkwknonewknonevdd_extdesc: pg position 1 | sport2 channel a frame sync | timer0 timer 2 | can0 transmit. notes: no notes. table 15. adsp-bf60x designer quick reference (continued) signal name type driver type int term reset term reset drive hiber term hiber drive power domain description and notes
rev. 0 | page 47 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 pg_02 i/oa wkwknonewknonevdd_extdesc: pg position 2 | pwm1 channel a low side | rsi0 data 1 | eth1 transmit data 1. notes: has an optional internal pull-up resistor for use with rsi. see the rsi chapter in the processor hardware reference for more details. pg_03 i/oa wkwknonewknonevdd_extdesc: pg position 3 | pwm1 channel a high side | rsi0 data 0 | eth1 transmit data 0. notes: has an optional internal pull-up resistor for use with rsi. see the rsi chapter in the processor hardware reference for more details. pg_04 i/oa wkwknonewknonevdd_extdesc: pg position 4 | sport2 channel a clock | timer0 timer 1 | can0 receive | timer0 alternate capture input 2. notes: may be used to wake the processor from hibernate or deep sleep mode. pg_05 i/oa wkwknonewknonevdd_extdesc: pg position 5 | rsi0 command | eth1 transmit enable | pwm1 sync | acm0 external trigger 1. notes: has an optional internal pull-up resistor for use with rsi. see the rsi chapter in the processor hardware reference for more details. pg_06 i/o a wk wk none wk none vdd_ext desc: pg position 6 | rsi0 clock | sport2 channel b transmit data valid | eth1 reference clock | pwm1 shutdown input. notes: no notes. pg_07 i/oa wkwknonewknonevdd_extdesc: pg position 7 | sport2 channel b frame sync | timer0 timer 5 | cnt0 count zero marker. notes: no notes. pg_08 i/oa wkwknonewknonevdd_extdesc: pg position 8 | sport2 channel a data 1 | timer0 timer 3 | pwm1 shutdown input. notes: no notes. pg_09 i/oa wkwknonewknonevdd_extdesc: pg position 9 | sport2 channel a data 0 | timer0 timer 4. notes: no notes. pg_10 i/oa wkwknonewknonevdd_extdesc: pg position 10 | uart1 request to send | sport2 channel b clock. notes: no notes. pg_11 i/oa wkwknonewknonevdd_extdesc: pg position 11 | sport2 channel b data 1 | timer0 timer 6 | cnt0 count up and direction. notes: no notes. table 15. adsp-bf60x designer quick reference (continued) signal name type driver type int term reset term reset drive hiber term hiber drive power domain description and notes
rev. 0 | page 48 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 pg_12 i/o a wk wk none wk none vdd_ext desc: pg position 12 | sport2 channel b data 0 | timer0 timer 7 | cnt0 count down and gate. notes: no notes. pg_13 i/oa wkwknonewknonevdd_extdesc: pg position 13 | uart1 clear to send | timer0 clock. notes: no notes. pg_14 i/oa wkwknonewknonevdd_extdesc: pg position 14 | uart1 receive | sys core 1 idle indicator | timer0 alternate capture input 1. notes: no notes. pg_15 i/oa wkwknonewknonevdd_extdesc: pg position 15 | uart1 transmit | sys core 0 idle indicator | sys processor sleep indicator | timer0 alternate capture input 4. notes: no notes. smc0_a01 i/o a wk wk none wk none vdd_ext desc: smc0 address 1. notes: no notes. smc0_a02 i/o a wk wk none wk none vdd_ext desc: smc0 address 2. notes: no notes. smc0_ams0 i/o a pu pu none pu none vdd_ext desc: smc0 memory select 0. notes: no notes. smc0_aoe _ ? nordv i/o a wk wk none wk none vdd_ext desc: smc0 nor data valid | smc0 output enable. notes: no notes. smc0_ardy_ ? norwt i/o na none none none none none vdd_ext desc: smc0 nor wait | smc0 asynchronous ready. notes: requires an external pull-up resistor. smc0_are i/o a pu pu none pu none vdd_ext desc: smc0 read enable. notes: no notes. smc0_awe i/o a pu pu none pu none vdd_ext desc: smc0 write enable. notes: no notes. smc0_br i/o na none none none none none vdd_ext desc: smc0 bus request. notes: requires an external pull-up resistor. smc0_d00 i/o a wk wk none wk none vdd_ext desc: smc0 data 0. notes: no notes. smc0_d01 i/o a wk wk none wk none vdd_ext desc: smc0 data 1. notes: no notes. smc0_d02 i/o a wk wk none wk none vdd_ext desc: smc0 data 2. notes: no notes. smc0_d03 i/o a wk wk none wk none vdd_ext desc: smc0 data 3. notes: no notes. smc0_d04 i/o a wk wk none wk none vdd_ext desc: smc0 data 4. notes: no notes. smc0_d05 i/o a wk wk none wk none vdd_ext desc: smc0 data 5. notes: no notes. table 15. adsp-bf60x designer quick reference (continued) signal name type driver type int term reset term reset drive hiber term hiber drive power domain description and notes
rev. 0 | page 49 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 smc0_d06 i/o a wk wk none wk none vdd_ext desc: smc0 data 6. notes: no notes. smc0_d07 i/o a wk wk none wk none vdd_ext desc: smc0 data 7. notes: no notes. smc0_d08 i/o a wk wk none wk none vdd_ext desc: smc0 data 8. notes: no notes. smc0_d09 i/o a wk wk none wk none vdd_ext desc: smc0 data 9. notes: no notes. smc0_d10 i/o a wk wk none wk none vd d_ext desc: smc0 data 10. notes: no notes. smc0_d11 i/o a wk wk none wk none vd d_ext desc: smc0 data 11. notes: no notes. smc0_d12 i/o a wk wk none wk none vd d_ext desc: smc0 data 12. notes: no notes. smc0_d13 i/o a wk wk none wk none vd d_ext desc: smc0 data 13. notes: no notes. smc0_d14 i/o a wk wk none wk none vd d_ext desc: smc0 data 14. notes: no notes. smc0_d15 i/o a wk wk none wk none vd d_ext desc: smc0 data 15. notes: no notes. sys_bmode0 i/o na none none none none none vdd_ext desc: sys boot mode control 0. notes: no notes. sys_bmode1 i/o na none none none none none vdd_ext desc: sys boot mode control 1. notes: no notes. sys_bmode2 i/o na none none none none none vdd_ext desc: sys boot mode control 2. notes: no notes. sys_clkin a na none none none none none vdd_ext desc: sys clock input/crystal input. notes: active during reset. sys_clkout i/o a none none l none none vdd_ext desc: sys processor clock output. notes: no notes. sys_extwake i/o a none none h none l vdd_ext desc: sys external wake control. notes: drives low during hibernate and high all other times. sys_fault i/o a none none none none none vdd_ext desc: sys fault. notes: open source, requires an external pull-down resistor. sys_fault i/o a none none none none none vdd_ext desc: sys complementary fault. notes: open drain, requires an external pull-up resistor. sys_hwrst i/o na none none none none none vdd_ext desc: sys processor hardware reset control. notes: active during reset. sys_nmi_ ? resout i/o a none none l none none vdd_ext desc: sys reset output | sys non- maskable interrupt. notes: requires an external pull-up resistor. table 15. adsp-bf60x designer quick reference (continued) signal name type driver type int term reset term reset drive hiber term hiber drive power domain description and notes
rev. 0 | page 50 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 sys_pwrgd i/o na none none none none none vdd_ext desc: sys power good indicator. notes: if hibernate is not used or the internal power good counter is used, connect to vdd_ext. sys_tda a na none none none none none vdd_td desc: sys thermal diode anode. notes: active during reset and hibernate. if the thermal diode is not used, connect to ground. sys_tdk a na none none none none none vdd_td desc: sys thermal diode cathode. notes: active during reset and hibernate. if the thermal diode is not used, connect to ground. sys_xtal a na none none none none none vdd_ext desc: sys crystal output. notes: leave unconnected if an oscillator is used to provide sys_clkin. active during reset. state during hibernate is controlled by dpm_hib_dis. twi0_scl i/o d none none none none none vd d_ext desc: twi0 serial clock. notes: open drain, requires external pull- up resistor. consult version 2.1 of the i2c specification for the proper resistor value. if twi is not used, connect to ground. twi0_sda i/o d none none none none none vd d_ext desc: twi0 serial data. notes: open drain, requires external pull- up resistor. consult version 2.1 of the i2c specification for the proper resistor value. if twi is not used, connect to ground. twi1_scl i/o d none none none none none vd d_ext desc: twi1 serial clock. notes: open drain, requires external pull- up resistor. consult version 2.1 of the i2c specification for the proper resistor value. if twi is not used, connect to ground. twi1_sda i/o d none none none none none vd d_ext desc: twi1 serial data. notes: open drain, requires external pull- up resistor. see the i2c-bus specification, version 2.1, january 2000 for the proper resistor value. if twi is not used, connect to ground. usb0_clkin a na none none none none none vdd _usb desc: usb0 clock/crystal input. notes: if usb is not used, connect to ground. active during reset. usb0_dm i/o f none none none none none vdd_usb desc: usb0 data C. notes: pull low if not using usb. for complete documentation of hibernate behavior when usb is used, see the usb chapter in the processor hardware reference. table 15. adsp-bf60x designer quick reference (continued) signal name type driver type int term reset term reset drive hiber term hiber drive power domain description and notes
rev. 0 | page 51 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 usb0_dp i/o f none none none none none vdd_usb desc: usb0 data +. notes: pull low if not using usb. for complete documentation of hibernate behavior when usb is used, see the usb chapter in the processor hardware reference. usb0_id i/o na none none none pu none vdd_usb desc: usb0 otg id. notes: if usb is not used, connect to ground. when usb is being used, the internal pull-up resistor that is present during hibernate is programmable. see the usb chapter in the processor hardware reference. active during reset. usb0_vbc i/o e none none none none none vd d_usb desc: usb0 vbus control. notes: if usb is not used, pull low. usb0_vbus i/o g none none none none none vdd_usb desc: usb0 bus voltage. notes: if usb is not used, connect to ground. vdd_dmc s na none none none none none na desc: vdd for dmc. notes: if the dmc is not used, connect to vdd_int. vdd_ext s na none none none none none na desc: external vdd. notes: must be powered. vdd_int s na none none none none none na desc: internal vdd. notes: must be powered. vdd_td s na none none none none none n a desc: vdd for thermal diode. notes: if the thermal diode is not used, connect to ground. vdd_usb s na none none none none none na desc: vdd for usb. notes: if usb is not used, connect to vdd_ ext. vref_dmc s na none none none none none na desc: vref for dmc. notes: if the dmc is not used, connect to vdd_int. table 15. adsp-bf60x designer quick reference (continued) signal name type driver type int term reset term reset drive hiber term hiber drive power domain description and notes
rev. 0 | page 52 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 specifications for information about product specifications please contact your adi representative. operating conditions parameter conditions min nominal max unit v dd_int internal supply voltage cclk 500 mhz 1.19 1.25 1.32 v v dd_ext 1 1 must remain powered (even if the as sociated function is not used). external supply voltage 1.7 1.8 1.9 v v dd_ext 1 external supply voltage 3.13 3.3 3.47 v v dd_dmc ddr2/lpddr supply voltage 1.7 1.8 1.9 v v dd_usb 2 2 if not used, connect to 1.8 v or 3.3 v. usb supply voltage 3.13 3.3 3.47 v v dd_td thermal diode supply voltage 3.13 3.3 3.47 v v ih 3 3 parameter value applies to all input an d bidirectional signals except twi signals, dmc0 signals and usb0 signals. high level input voltage v dd_ext = 3.47 v 2.1 v v ih 3 high level input voltage v dd_ext = 1.9 v 0.7 v dd_ext v v ihtwi 4, 5 4 parameter applies to twi signals. 5 twi signals are pulled up to v bustwi . see table 16 . high level input voltage v dd_ext = maximum 0.7 v vbustwi v vbustwi v v ih_ddr2 6, 7 6 parameter applies to dmc0 signals in ddr2 mode. 7 v ddr_ref is the voltage applied to pin v ref_dmc , nominally v dd_dmc /2. v dd_dmc = 1.9 v v ddr_ref + 0.25 v v ih_lpddr 8 8 parameter applies to dmc0 signals in lpddr mode. v dd_dmc = 1.9 v 0.8 v dd_dmc v v id_ddr2 9 9 parameter applies to signals dmc0_ck, dmc0_ck , dmc0_ldqs, dmc0_ldqs , dmc0_udqs, dmc0_udqs when used in ddr2 differential input mode. differential input voltage v ix = 1.075 v 0.50 v v id_ddr2 9 differential input voltage v ix = 0.725 v 0.55 v v il 3 low level input voltage v dd_ext = 3.13 v 0.8 v v il 3 low level input voltage v dd_ext = 1.7 v 0.3 v dd_ext v v iltwi 4, 5 low level input voltage v dd_ext = minimum 0.3 v vbustwi v v il_ddr2 6, 7 v dd_dmc = 1.7 v v ddr_ref C 0.25 v v il_lpddr 8 v dd_dmc = 1.7 v 0.2 v dd_dmc v t j junction temperature t ambient = C40c to +85c C40 +105 c t j junction temperature t ambient = C40c to +105c C40 +125 c table 16. twi_vsel selections and v dd_ext /v bustwi v dd_ext nominal v bustwi min v bustwi nom v bustwi max unit twi000 1 1 designs must comply with the v dd_ext and v bustwi voltages specified for the default twi_dt setting for correct jtag boundary scan operation during reset. 3.300 3.135 3.300 3.465 v twi001 1.800 1.700 1.800 1.900 v twi011 1.800 3.135 3.300 3.465 v twi100 3.300 4.750 5.000 5.250 v
rev. 0 | page 53 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 clock related operating conditions table 17 describes the core clock ti ming requirements. the data presented in the tables applies to all speed grades (found in automotive products on page 109 ) except where expressly noted. figure 8 provides a graphical repr esentation of the vari- ous clocks and their available divider values. table 17. clock operating conditions parameter min max unit f cclk core clock frequency (cclk sysclk) 500 mhz f sysclk sysclk frequency 250 mhz f sclk0 1 sclk0 frequency (sysclk sclk0) 30 125 mhz f sclk1 sclk1 frequency (sysclk sclk1) 125 mhz f dclk ddr2/lpddr clock frequenc y (sysclk dclk) 250 mhz f oclk output clock frequency 125 mhz f pvpclk pvp clock frequency 83.3 mhz 1 the minimum frequency for sclk0 appl ies only when the usb is used. table 18. phase-locked loop operating conditions parameter min max unit f pllclk pll clock frequency 250 1000 mhz figure 8. clock relationships and divider values sys_clkin pll dclk sysclk cclk sclk1 (sports, spi, acm) sclk0 (pvp, all other peripherals) csel (1 - 32) syssel (1 - 32) s0sel (1 - 4) s1sel (1 - 4) dsel (1 - 32) oclk osel (1 - 128) pllclk
rev. 0 | page 54 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 electrical characteristics parameter test conditions min typical max unit v oh 1 high level output voltage v dd_ext = 1 . 7 v, i oh = C0.5 ma v dd_ext C 0.40 v v oh 1 high level output voltage v dd_ext = 3 . 1 3 v, i oh = C0.5 ma v dd_ext C 0.40 v v oh_ddr2 2 high level output voltage, ds = 00 v dd_dmc = 1.70 v, i oh = C13.4 ma 1.388 v v oh_ddr2 3 high level output voltage, ds = 10 v dd_dmc = 1.70 v, i oh = C6.70 ma 1.311 v v oh_lpddr 4 high level output voltage, ds = 00 v dd_dmc = 1.70 v, i oh = C11.2 ma 1.300 v v oh_lpddr 5 high level output voltage, ds = 01 v dd_dmc = 1.70 v, i oh = C7.85 ma 1.300 v v oh_lpddr 6 high level output voltage, ds = 10 v dd_dmc = 1.70 v, i oh = C5.10 ma 1.300 v v oh_lpddr 7 high level output voltage, ds = 11 v dd_dmc = 1.70 v, i oh = C2.55 ma 1.300 v v ol 8 low level output voltage v dd_ext = 1 . 7 v, i ol = 2.0 ma 0.400 v v ol 8 low level output voltage v dd_ext = 3.13 v, i ol = 2.0 ma 0.400 v v ol_ddr2 2 low level output voltage, ds = 00 v dd_dmc = 1.70 v, i ol 13.4 ma 0.312 v v ol_ddr2 3 low level output voltage, ds = 10 v dd_dmc = 1.70 v, i ol = 6.70 ma 0.390 v v ol_lpddr 4 low level output voltage, ds = 00 v dd_dmc = 1.70 v, i ol = 11.2 ma 0.400 v v ol_lpddr 5 low level output voltage, ds = 01 v dd_dmc = 1.70 v, i ol = 7.85 ma 0.400 v v ol_lpddr 6 low level output voltage, ds = 10 v dd_dmc = 1.70 v, i ol = 5.10 ma 0.400 v v ol_lpddr 7 low level output voltage, ds = 11 v dd_dmc = 1.70 v, i ol = 2.55 ma 0.400 v i ih 9 high level input current v dd_ext = 3.47 v, v dd_dmc = 1.9 v, v dd_ usb = 3.47 v, v in = 3.47 v 10 a i ih_pd 10 high level input current with pull- down resistor v dd_ext = 3.47 v, v dd_dmc = 1.9 v, v dd_ usb = 3.47 v, v in = 3.47 v 110 a i il 11 low level input current v dd_ext = 3.47 v, v dd_dmc = 1.9 v, v dd_ usb = 3.47 v, v in = 0 v 10 a i il_pu 12 low level input current with pull-up resistor v dd_ext = 3.47 v, v dd_dmc = 1.9 v, v dd_ usb = 3.47 v, v in = 0 v 100 a i ih_usb0 13 high level input current v dd_ext = 3.47 v, v dd_dmc = 1.9 v, v dd_ usb = 3.47 v, v in = 3.47 v 240 a i il_usb0 13 low level input current v dd_ext = 3.47 v, v dd_dmc = 1.9 v, v dd_ usb = 3.47 v, v in = 0 v 100 a i ozh 14 three-state leakage current v dd_ext = 3.47 v, v dd_dmc = 1.9 v, v dd_ usb = 3.47 v, v in = 3.47 v 10 a i ozh 15 three-state leakage current v dd_ext = 3.47 v, v dd_dmc = 1.9 v, v dd_ usb = 3.47 v, v in = 1.9 v 10 a i ozl 16 three-state leakage current v dd_ext = 3.47 v, v dd_dmc = 1.9 v, v dd_ usb = 3.47 v, v in = 0 v 10 a i ozl_pu 17 three-state leakage current with pull-up resistor v dd_ext = 3.47 v, v dd_dmc = 1.9 v, v dd_ usb = 3.47 v, v in = 0 v 100 a i ozh_twi 18 three-state leakage current v dd_ext = 3.47 v, v dd_dmc = 1.9 v, v dd_ usb = 3.47 v, v in = 5.5 v 10 a c in 19, 20 input capacitance t ambient = 25c 4.9 6.7 pf c in_twi 18, 20 input capacitance t ambient = 25c 8.9 9.9 pf c in_ddr 20, 21 input capacitance t ambient = 25c 5.8 6.6 pf i dd_td v dd_td current v dd_td = 3.3 v 1 a i dd_deepsleep 22, 23 v dd_int current in deep sleep mode f cclk = 0 mhz f sclk0/1 = 0 mhz table 21 on page 57 ma
rev. 0 | page 55 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 i dd_idle 23 v dd_int current in idle f cclk = 500 mhz asfc0 = 0.14 (idle) asfc1 = 0 (disabled) f sysclk = 250 mhz, f sclk0/1 = 125 mhz f dclk = 0 mhz (ddr disabled) f usbclk = 0 mhz (usb disabled) no pvp or dma activity t j = 25c 137 ma i dd_typ 23 v dd_int current f cclk = 500 mhz asfc0 = 1.0 (full-on typical) asfc1 = 0.86 (app) f sysclk = 250 mhz, f sclk0/1 = 125 mhz f dclk = 250 mhz f usbclk = 0 mhz (usb disabled) dma data rate = 124 mb/s medium pvp activity t j = 25c 357 ma i dd_hibernate 22, 24 hibernate state current v dd_int = 0 v, v dd_ext = v dd_td = v dd_usb = 3.3 v, v dd_dmc = 1.8 v, v ref_dmc = 0.9 v, t j = 25c, f clkin = 0 mhz 40 ? a i dd_hibernate 22, 24 hibernate state current without usb v dd_int = 0 v, v dd_ext = v dd_td = v dd_usb = 3.3 v, v dd_dmc = 1.8 v, v ref_dmc = 0.9 v, t j = 25c, f clkin = 0 mhz, usb protection disabled (usb0_phy_ctl.dis=1) 10 ? a i dd_int 23 v dd_int current f cclk > 0 mhz f sclk0/1 0 mhz see i ddint_tot equation on page 56 ma 1 applies to all output and bidirecti onal signals except dm c0 signals, twi signals and usb0 signals. 2 applies to all dmc0 output and bidirectiona l signals in ddr2 full drive strength mode. 3 applies to all dmc0 output an d bidirectional signals in ddr2 half drive strength mode. 4 applies to all dmc0 output and bidirectiona l signals in lpddr full drive strength mode. 5 applies to all dmc0 output and bidirectional signals in lpddr three-quarter drive strength mode. 6 applies to all dmc0 output an d bidirectional signals in lpdd r half drive strength mode. 7 applies to all dmc0 output and bidirectional signals in lpddr one-quarter drive strength mode. 8 applies to all output and bid irectional signals except dmc0 signals and usb0 signals. 9 applies to signals smc0_ardy, smc0_br , sys_bmode0C2, sys_clkin, sys_hwrst, sys_pwrgd, jtg_tdi, and jtg_tms . 10 applies to signals jtg_tck and jtg_trst . 11 applies to signals smc0_ardy, smc0_br , sys_bmode0C2, sys_clkin, sys_hwrst, sys_pwrgd, jtg_tck, and jtg_trst . 12 applies to signals jtg_tdi, jtg_tms. 13 applies to sign al usb0_clkin. 14 applies to signals pa0C15, pb0C15, pc0C15, pd0C15, pe0C15, pf0C15, pg0C15, smc0_ams0 , smc0_are , smc0_awe , smc0_a0e , smc0_a01C02, smc0_d00C15, sys_ fault, sys_fault , jtg_emu , jtg_tdo, usb0_dm, usb0_dp, usb0_id, usb0_vbc, usb0_vbus. 15 applies to dmc0_a[00:13], dmc0_ba[0:2], dmc0_cas , dmc0_cs0 , dmc0_dq[00:15], dmc0_lqds, dmc0_ldqs , dmc0_udqs, dmc0_udqs , dmc0_ldm, dmc0_udm, dmc0_odt, dmc0_ras , and dmc0_we . 16 applies to signals pa0C15, pb0C15, pc0C15, pd0C15, pe0C15, pf0C15, pg0C15, smc0_a0e , smc0_a01C02, smc0_d00C15, sys_fault, sys_fault , jtg_emu , jtg_ tdo, usb0_dm, usb0_dp, usb0_i d, usb0_vbc, usb0_vbus, dmc0 _a00C13, dmc0_ba0C2, dmc0_cas , dmc0_cs0 , dmc0_dq00C15, dmc0_lqds, dmc0_ ldqs , dmc0_udqs, dmc0_udqs , dmc0_ldm, dmc0_udm, dmc0_odt, dmc0_ras , dmc0_we , and twi signals. 17 applies to signals smc0_ams0 , smc0_are , smc0_awe , and when rsi pull-up resistors are enabled, pe10C13, 15 and pg00, 02, 03, 05. 18 applies to all twi signals. 19 applies to all signals, except dmc0 and twi signals. 20 guaranteed, but not tested. 21 applies to all dmc0 signals 22 see the adsp-bf60x blackfin processor hardware reference manual for definition of deep sleep and hibernate operating modes. 23 additional information can be found at total internal power dissipation on page 56 . 24 applies to v dd_ext , v dd_dmc , v dd_usb and v dd_td supply signals only. clock inputs are tied high or low. parameter test conditions min typical max unit
rev. 0 | page 56 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 total internal power dissipation total power dissipation has two components: 1. static, including leakage current (deep sleep) 2. dynamic, due to tr ansistor switching characteristics for each clock domain many operating conditions can also affect po wer dissipation, including temperature, voltage, operating frequency, and pro- cessor activity. the following eq uation describes the internal current consumption. i ddint_tot = i ddint_cclk_dyn + i ddint_sysclk_dyn + ? i ddint_sclk0_dyn + i ddint_sclk1_dyn + i ddint_dclk_dyn + ? i ddint_usbclk_dyn + i ddint_dma_dr_dyn + ? i ddint_deepsleep + i ddint_pvp_dyn i ddint_deepsleep is the only item present th at is part of the static power dissipation component. i ddint_deepsleep is specified as a function of voltage (v dd_int ) and temperature (see table 21 ). there are eight different items that contribute to the dynamic power dissipation. these componen ts fall into three broad cate- gories: application-dependent currents, clock currents and data transmission currents. application-dependent current the application-dependent curr ents include the dynamic cur- rent in the core clock domain and the dynamic current of the pvp. core clock (cclk) use is subject to an activity scaling factor (asf) that represents applicatio n code running on the processor cores and l1/l2 memories ( table 20 ). the asf is combined with the cclk frequency and v dd_int dependent data in table 19 to calculate this portion. i ddint_cclk_dyn (ma) = table 19 (asfc0 + asfc1) the dynamic current of the pvp is determined by selecting the appropriate use case from table 22 . i ddint_pvp_dyn (ma) = table 22 clock current the dynamic clock currents provid e the total power dissipated by all transistors switching in the clock paths. the power dissi- pated by each clock domain is dependent on voltage (v dd_int ), operating frequency and a unique scaling factor. i ddint_sysclk_dyn (ma) = 0.187 f sysclk (mhz) v dd_int (v) i ddint_sclk0_dyn (ma) = 0.217 f sclk0 (mhz) v dd_int (v) i ddint_sclk1_dyn (ma) = 0.042 f sclk1 (mhz) v dd_int (v) i ddint_dclk_dyn (ma) = 0.024 f dclk (mhz) v dd_int (v) the dynamic component of the usb clock is a unique case. the usb clock contributes a near constant current value when used. i ddint_usbclk_dyn (ma) = 5 ma (if usb enabled) data transmission current the data transmission current represents the power dissipated when transmitting data. this cu rrent is expressed in terms of data rate. the calculation is performed by adding the data rate (mb/s) of each dma and core dr iven access to peripherals and l2/external memory. this number is then multiplied by a coeffi- cient and v dd_int . the following equation provides an estimate of all data transmission current. i ddint_dma_dr_dyn (ma) = 0.0578 data rate (mb/s) v dd_int (v) for details on using this equation see the related engineer zone material. table 19. cclk dynamic current per core (ma, with asf = 1) f cclk (mhz) voltage (v dd_int ) 1.175 1.200 1.225 1.250 1.275 1.300 1.320 500 96.3 98.8 101.5 103.9 106.7 109.3 110.8 450 87.2 89.5 91.9 94.1 96.7 98.9 100.6 400 78.0 80.1 82.2 84.3 86.5 88.6 90.1 350 68.7 70.7 72.5 74.4 76.3 78.3 79.4 300 59.7 61.2 63.0 64.6 66.3 68.0 69.1 250 50.3 51.8 53.2 54.7 56.3 57.6 58.5 200 41.3 42.4 43.6 44.8 46.0 47.2 48.2 150 32.0 32.9 34.0 34.8 35.9 37.0 37.4 100 22.7 23.5 24.2 25.0 25.7 26.5 26.9
rev. 0 | page 57 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 table 20. activity scaling factors (asf) i ddint power vector asf i dd-peak 1.34 i dd-high 1.25 i dd-full-on-typ 1.00 i dd-app 0.86 i dd-nop 0.72 i dd-idle 0.14 table 21. static currenti dd_deepsleep (ma) t j (c) voltage (v dd_int ) 1.175 1.200 1.225 1.250 1.275 1.300 1.320 C40 1.7 1.8 2.2 2.5 2.7 3.1 3.4 C20 4.0 4.2 4.6 5.1 5.6 6.2 6.8 0 8.2 9.0 9.6 10.6 11.5 12.5 13.4 25 18.3 19.8 21.5 23.2 25.3 27.2 29.0 40 29.6 31.7 34.4 36.8 40.0 42.8 45.4 55 45.4 48.9 52.4 56.4 60.6 65.0 68.1 70 65.8 70.4 75.5 80.6 86.2 92.4 97.9 85 92.8 99.3 105.9 113.0 120.7 128.9 136.4 100 135.5 144.2 153.6 163.4 173.9 185.1 194.1 105 152.7 162.4 172.5 183.4 195.2 207.5 217.5 115 191.9 203.7 216.2 229.5 243.9 258.6 271.1 125 232.8 247.2 261.8 277.3 294.0 311.9 326.4 table 22. i ddint_pvp_dyn (ma) pvp activity level pvpsf (pvp scaling factor) high 42.4 medium 20 low 0
rev. 0 | page 58 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 processor absolute maximum ratings stresses greater than those listed in table 23 may cause perma- nent damage to the device. these are stress ratings only. functional operation of the device at these or any other condi- tions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd sensitivity processor package information the information presented in figure 9 and table 25 provides details about package branding. for a complete listing of prod- uct availability, see automotive products on page 109 . table 23. absolute maximum ratings parameter rating internal supply voltage (v dd_int ) C0.33 v to 1.32 v external (i/o) supply voltage (v dd_ext ) C0.33 v to 3.63 v thermal diode supply voltage ? (v dd_td ) C0.33 v to 3.63 v ddr2 controller supply voltage ? (v dd_dmc ) C0.33 v to 1.90 v usb phy supply voltage (v dd_usb ) C0.33 v to 3.63 v input voltage 1, 2, 3 1 applies to 100% transient duty cycle. 2 applies only when v dd_ext is within spec ifications. when v dd_ext is outside specifications, the range is v dd_ext 0.2 v. 3 for other duty cycles see table 24 . C0.33 v to 3.63 v twi input voltage 2, 4 4 applies to balls twi_scl and twi_sda. C0.33 v to 5.50 v usb0_dx input voltage 5 5 if the usb is not used, connect us b0_dx and usb0_vbu s according to table 15 on page 37 . C0.33 v to 5.25 v usb0_vbus input voltage 5 C0.33 v to 6.00 v ddr2 input voltage 6 6 applies only when v dd_dmc is within specifications. when v dd_dmc is outside specifications, the range is v dd_dmc 0.2 v. C0.33 v to 1.90 v output voltage swing C0.33 v to v dd_ext + 0.5 v i oh /i ol current per signal 1 12.5 ma (max) storage temperature range C65c to +150c junction temperature under bias +125c table 24. maximum duty cycle for input transient volt- age 1, 2 1 applies to all signal ba lls with the exception of sys_clkin, sys_xtal, ? sys_ext_wake, usb0_dp, usb0_dm, usb0_vbus, twi signals, and dmc0 signals. 2 applies only when v dd_ext is within specif ications. when v dd_ext is outside speci- fications, the range is v dd_ext 0.2 v. maximum duty cycle (%) 2 v in min (v) 3 3 the individual values cannot be combined for analysis of a single instance of overshoot or undershoot. the worst case observed value must fall within one of the specified voltages, and the total duration of the overshoot or undershoot (exceeding the 100% case) must be less th an or equal to the corresponding duty cycle. v in max (v) 3 100 C0.33 3.63 50 C0.50 3.80 40 C0.56 3.86 25 C0.67 3.97 20 C0.73 4.03 15 C0.80 4.10 10 C0.90 4.20 figure 9. product information on package table 25. package brand information brand key field description adsp-bf609 product model t temperature range pp package type z rohs compliant designation ccc see ordering guide vvvvvv.x assembly lot code n.n silicon revision yyww date code esd (electrostatic discharge) sensitive device. charged devices and circuit boards can discharge without detection. although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy esd. therefore, proper esd precautions should be taken to avoid performance degradation or loss of functionality. tppccc ads a yyww countryoforigin vvvvvv. n.n
rev. 0 | page 59 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 timing specifications specifications are subject to change without notice. clock and reset timing table 26 and figure 10 describe clock and reset operations. per the cclk, sysclk, sclk0, sclk 1, dclk, and oclk timing specifications in table 17 on page 53 , combinations of ? sys_clkin and clock multipliers mu st not select clock rates in excess of the processors maximum instruction rate. table 26. clock and reset timing v dd_ext 1.8 v/3.3 v nominal parameter min max unit timing requirements f ckin sys_clkin frequency (using a crystal) 1, 2, 3 20 50 mhz f ckin sys_clkin frequency (using a crystal oscillator) 1, 2, 3 20 60 mhz t ckinl sys_clkin low pulse 1 6.67 ns t ckinh sys_clkin high pulse 1 6.67 ns t wrst sys_hwrst asserted pulse width low 4 11 t ckin ns 1 applies to pll bypass mode and pll non bypass mode. 2 the t ckin period (see figure 10 ) equals 1/f ckin . 3 if the cgu_ctl.df bit is set, the minimum f ckin specification is 40 mhz. 4 applies after power-up se quence is complete. see table 27 and figure 11 for power-up reset timing. figure 10. clock and reset timing sys_clkin t wrst t ckin t ckinl t ckinh sys_hwrst
rev. 0 | page 60 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 power-up reset timing in figure 11, v dd_supplies are v dd_int , v dd_ext , v dd_dmc , v dd_usb , and v dd_td . table 27. power-up reset timing parameter min max unit timing requirement t rst_in_pwr sys_hwrst deasserted after v dd_int , v dd_ext , v dd_dmc , v dd_usb , v dd_td , and sys_ clkin are stable and within specification 11 t ckin ns figure 11. power- up reset timing reset t rst_in_pwr clkin v dd_supplies
rev. 0 | page 61 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 asynchronous read table 28. asynchronous memory read (bxmode = b#00) v dd_ext 1.8 v/3.3 v nominal parameter min max unit timing requirements t sdatare data in setup before smc0_are high 8.2 ns t hdatare data in hold after smc0_are high 0 ns t dardyare smc0_ardy valid after smc0_are low 1, 2 (rat C 2.5) t sclk0 C 17.5 ns switching characteristics t addrare smc0_ax/smc0_amsx assertion before smc0_ are low 3 (prest + rst + preat) t sclk0 C 2 ns t aoeare smc0_aoe assertion before smc0_are low (rst + preat) t sclk0 C 2 ns t hare output 4 hold after smc0_are high 5 rht t sclk0 C2 ns t ware smc0_are active low width 6 rat t sclk0 C 2 ns t dareardy smc0_are high delay after smc0_ardy assertion 1 2.5 t sclk0 3.5 t sclk0 + 17.5 ns 1 smc0_bxctl.ardyen bit = 1. 2 rat value set using the smc_bxtim.rat bits. 3 prest, rst, and preat values set using the smc_bxetim.pre st bits, smc_bxtim.rst bits, and the smc_bxetim.preat bits. 4 output signals are smc0_ax, smc0_ams , smc0_aoe , smc0_abex . 5 rht value set using the smc_bxtim.rht bits. 6 smc0_bxctl.ardyen bit = 0. figure 12. asynchronous read smc0_are smc0_amsx smc0_ax t ware smc0_aoe smc0_dx (data) smc0_ardy t aoeare t addrare t dardyare t hare t hdatare t dareardy t sdatare
rev. 0 | page 62 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 asynchronous flash read table 29. asynchronous flash read v dd_ext 1.8 v/3.3 v nominal parameter min max unit switching characteristics t amsadv smc0_ax (address)/smc0_amsx assertion before smc0_nordv low 1 prest t sclk0 C 2 ns t wadv smc0_nordv active low width 2 rst t sclk0 C 2 ns t dadvare smc0_are low delay from smc0_nordv high 3 preat t sclk0 C 2 ns t hare output 4 hold after smc0_are high 5 rht t sclk0 C 2 ns t ware 6 smc0_are active low width 7 rat t sclk0 C 2 ns 1 prest value set using the smc_bxetim.prest bits. 2 rst value set using the smc_bxtim.rst bits. 3 preat value set using th e smc_bxetim.preat bits. 4 output signals are smc0_ax, smc0_ams , smc0_aoe . 5 rht value set using the smc_bxtim.rht bits. 6 smc0_bxctl.ardyen bit = 0. 7 rat value set using the smc_bxtim.rat bits. figure 13. asynchronous flash read smc0_ax t amsadv t dadvare t wadv t ware t hare read latched data smc0_amsx (nor_ce) smc0_nordv smc0_are (nor_oe) smc0_dx (data)
rev. 0 | page 63 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 asynchronous page mode read table 30. asynchronous page mode read v dd_ext 1.8 v /3.3 v nominal parameter min max unit switching characteristics t av smc0_ax (address) valid for first address min width 1 (prest + rst + preat + rat) t sclk0 C 2 ns t av1 smc0_ax (address) valid for subsequent smc0_ax (address) min width pgws t sclk0 C 2 ns t wadv smc0_nordv active low width 2 rst t sclk0 C 2 ns t hare output 3 hold after smc0_are high 4 rht t sclk0 C 2 ns t ware 5 smc0_are active low width 6 rat t sclk0 C 2 ns 1 prest, rst, preat and rat values set using the smc_bxetim.prest bits, smc_bxtim.rst bits, smc_bx etim.preat bits, and the smc_bx tim.rat bits. 2 rst value set using th e smc_bxtim.rst bits. 3 output signals are smc0_ax, smc0_amsx , smc0_aoe . 4 rht value set using the smc_bxtim.rht bits. 5 smc_bxctl.ardyen bit = 0. 6 rat value set using the smc_bxtim.rat bits. figure 14. asynchronous page mode read smc0_amsx (nor_ce) smc0_are (nor_oe) smc0_aoe nor_adv smc0_dx (data) a0 t wadv t ware t hare d0 d1 d2 d3 a0 + 1 a0 + 2 a0 + 3 t av t av1 t av1 t av1 read latched data read latched data read latched data read latched data smc0_ax (address)
rev. 0 | page 64 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 synchronous burst flash read table 31. synchronous burst ac timing (bxmode = b#11) v dd_ext 1.8 v/3.3 v nominal parameter min max unit timing requirements t nds data-in setup before smc0_norclk high 3 ns t ndh data-in hold after smc0_norclk high 1.5 ns t nws wait-in setup before smc0_norclk high 3 ns t nwh wait-in hold after smc0_norclk high 1.5 ns switching characteristics t nrcls nor_clk low period 1, 2 [0.5 bclk t sclk0 C 1] or [7] ns t nrchs nor_clk high period 1, 2 [0.5 bclk t sclk0 C 1] or [7] ns t nrclk nor_clk period 1, 2 [bclk t sclk0 C 1] or [15] ns t ndo output delay after smc0_norclk high 3 6n s t nho output hold after smc0_norclk high 3 0.8 ns 1 whichever is greater. 2 bclkdiv value set using th e smc_bxctl.bclk bits. bclk div = (smc_bxctl.bclk + 1). 3 output = smc0_ax (address), smc0_nordv, smc0_are , smc0_amsx (n0r_ce). figure 15. synchronous burst ac interface timing t ndo t nws t nwh t ndh t ndh t nds t nds t nho dn dn+1 dn+2 dn+3 smc0_amsx smc0_norclk smc0_ax (address) smc0_are nor_oe note: smc0_norclk dotted line represents a free running version of smc0_norclk that is not visible on the smc0_norclk pin. smc0_abe1 - 0 smc0_dx (data) smc0_nordv smc0_aoe smc0_norwt t ndo t ndo t ndo t ndo t ndo t ndo t ndo t nho t nrcls t nrclk t nrchs
rev. 0 | page 65 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 asynchronous write table 32. asynchronous memory write (bxmode = b#00) v dd_ext 1.8 v/3.3 v nominal parameter min max unit timing requirement t dardyawe 1 smc0_ardy valid after smc0_awe low 2 (wat C 2.5) t sclk0 C 17.5 ns switching characteristics t endat data enable after smc0_amsx assertion C3 ns t ddat data disable after smc0_amsx deassertion 3 ns t amsawe smc0_ax/smc0_amsx assertion before smc0_awe low 3 (prest + wst + preat) t sclk0 C 2 ns t hawe output 4 hold after smc0_awe high 5 wht t sclk0 C 2 ns t wawe 6 smc0_awe active low width 2 wat t sclk0 C 2 ns t daweardy 1 smc0_awe high delay after smc0_ardy assertion 2.5 t sclk0 3.5 t sclk0 + 17.5 ns 1 smc_bxctl.ardyen bit = 1. 2 wat value set using the smc_bxtim.wat bits. 3 prest, wst, preat values set using the smc_bxetim.prest bits, smc_bxtim.wst bits, smc_bxetim.pre at bits, and the smc_bxtim.rat bits. 4 output signals are data, smc0_ax, smc0_amsx , smc0_abex . 5 wht value set using the smc_bxtim.wht bits. 6 smc_bxctl.ardyen bit = 0. figure 16. asynchronous write smc0_awe smc0_abex smc0_ax t dardyawe t amsawe t daweardy t endat t ddat t hawe t wawe smc0_amsx smc0_dx (data) smc0_ardy
rev. 0 | page 66 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 asynchronous flash write all accesses table 33. asynchronous flash write v dd_ext 1.8 v/3.3 v nominal parameter min max unit switching characteristics t amsadv smc0_ax/smc0_amsx assertion before adv low 1 prest t sclk0 C 2 ns t dadvawe smc0_awe low delay from adv high 2 preat t sclk0 C 2 ns t wadv nr_adv active low width 3 wst t sclk0 C 2 ns t hawe output 4 hold after smc0_awe high 5 wht t sclk0 C 2 ns t wawe 6 smc0_awe active low width 7 wat t sclk0 C 2 ns 1 prest value set using the smc_bxetim.prest bits. 2 preat value set using th e smc_bxetim.preat bits. 3 wst value set using the smc_bxtim.wst bits. 4 output signals are data, smc0_ax, smc0_amsx , smc0_abex . 5 wht value set using the smc_bxtim.wht bits. 6 smc_bxctl.ardyen bit = 0. 7 wat value set using the smc_bxtim.wat bits. figure 17. asynchronous flash write nr_ce (smc0_amsx) nr_we (smc0_awe) nor_a 25 - 1 (smc0_ax) nr_adv (smc0_aoe) t amsadv t dadvawe nr_dq 15 - 0 (smc0_dx) t wadv t wawe t hawe table 34. all accesses v dd_ext 1.8 v/3.3 v nominal parameter min max unit switching characteristic t turn smc0_amsx inactive width (it + tt) t sclk0 C 2 ns
rev. 0 | page 67 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 bus request/bus grant ddr2 sdram clock and control cycle timing table 35. bus request/bus grant v dd_ext 1.8 v/3.3 v nominal parameter min max unit switching characteristics t dbgbr smc0_bg delay after smc0_br 2.5 t sclk0 3.5 t sclk0 + 17.5 ns t engdat data enable after smc0_bg deassertion C3 ns t dbgdat data disable after smc0_bg assertion 3 ns figure 18. bus request/bus grant smc0_br smc0_bg t dbgbr smc0 data/address control t engdat t dngdat table 36. ddr2 sdram read cycle timing, v dd_dmc nominal 1.8 v 250 mhz parameter min max unit switching characteristics t ck clock cycle time (cl = 2 not supported) 4 ns t ch minimum clock pulse width 0.45 0.55 t ck t cl maximum clock pulse width 0.45 0.55 t ck t is control/address setup relative to dmc0_ck rise 350 ps t ih control/address hold relative to dmc0_ck rise 475 ps figure 19. ddr2 sdram cloc k and control cycle timing note: control = dmc0_cs0 , dmc0_cke, dmc0_ras, dmc0_cas , and dmc0_we. address = dmc0_a00 - 13, and dmc0_ba0 - 1. dmc0_ck address control t is t ih t ck t ch t cl dmc0_ck
rev. 0 | page 68 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 ddr2 sdram read cycle timing table 37. ddr2 sdram read cycle timing, v dd_dmc nominal 1.8 v 250 mhz 1 1 in order to ensure proper operation of the ddr2, a ll the ddr2 guidelines have to be strictly followed. parameter min max unit timing requirements t dv data valid window 1 ns t dqsq dmc0_dqs-dmc0_dq skew for dmc0_dqs and associated dmc0_ dq signals 0.35 ns t qh dmc0_dq, dmc0_dqs output hold time from dmc0_dqs 1.6 ns t rpre read preamble 0.9 t ck t rpst read postamble 0.4 t ck figure 20. ddr2 sdram controller input ac timing ddr2_clkx ddr2_dqsn t ac t rpre t dqsq t dqsq t qh t rpst ddr2_data ddr2_clkx ddr2_dqsn t dqsck t ck t ch t cl t as t ah ddr2_addr ddr2_ctl t qh
rev. 0 | page 69 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 ddr2 sdram write cycle timing table 38. ddr2 sdram write cycle timing, v dd_dmc nominal 1.8 v 250 mhz 1 1 in order to ensure proper operation of the ddr2, a ll the ddr2 guidelines have to be strictly followed. parameter min max unit switching characteristics t dqss 2 2 write command to first dmc0_dqs delay = wl t ck + t dqss . dmc0_dqs latching rising transitions to associated clock edges C0.15 0.15 t ck t ds last data valid to dmc0_dqs delay 0.15 ns t dh dmc0_dqs to first data invalid delay 0.3 ns t dss dmc0_dqs falling edge to clock setup time 0.25 t ck t dsh dmc0_dqs falling edge hold time from dmc0_ck 0.25 t ck t dqsh dmc0_dqs input high pulse width 0.35 t ck t dqsl dmc0_dqs input low pulse width 0.35 t ck t wpre write preamble 0.35 t ck t wpst write postamble 0.4 t ck t ipw address and control output pulse width 0.6 t ck t dipw dmc0_dq and dmc0_dm output pulse width 0.35 t ck figure 21. ddr2 sdram controller output ac timing t ds t dh t dqss t dsh t dss t wpre t dqsl t dqsh t wpst dmc0_ldm dmc0_ck dmc0_a00 t ipw t dipw dmc0_udm dmc0_ldqs dmc0_udqs
rev. 0 | page 70 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 mobile ddr sdram clock and control cycle timing mobile ddr sdram read cycle timing table 39. mobile ddr sdram read cycle timing, v dd_dmc nominal 1.8 v 200 mhz parameter min max unit switching characteristics t ck clock cycle time (cl = 2 not supported) 5 ns t ch minimum clock pulse width 0.45 0.55 t ck t cl maximum clock pulse width 0.45 0.55 t ck t is control/address setup relative to dmc0_ck rise 1 ns t ih control/address hold relative to dmc0_ck rise 1 ns figure 22. mobile ddr sdram clock and control cycle timing table 40. mobile ddr sdram read cycle timing, v dd_dmc nominal 1.8 v 200 mhz parameter min max unit timing requirements t qh dmc0_dq, dmc0_dqs output hold time from dmc0_dqs 1.75 ns t dqsq dmc0_dqs-dmc0_dq skew for dmc0_dqs and associated dmc0_dq signals 0.4 ns t rpre read preamble 0.9 1.1 t ck t rpst read postamble 0.4 0.6 t ck figure 23. mobile ddr sdram controller input ac timing note: control = dmc0_cs0 , dmc0_cke, dmc0_ras, dmc0_cas , and dmc0_we. address = dmc0_a00 - 13, and dmc0_ba0 - 1. dmc0_ck address control t is t ih t ck t ch t cl dmc0_ck dmc0_ck dmc0_dqs t dqsq dmc0_dqs (data) dn dn+1 dn+2 dn+3 t rpre t rpst t qh
rev. 0 | page 71 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 mobile ddr sdram write cycle timing table 41. mobile ddr sdram write cycle timing, v dd_dmc nominal 1.8 v 200 mhz parameter min max unit switching characteristics t dqss 1 1 write command to first dmc0_dqs delay = wl t ck + t dqss . dmc0_dqs latching rising transition s to associated clock edges 0.75 1.25 t ck t ds last data valid to dmc0_dqs delay (slew > 1 v/ns) 0.48 ns t dh dmc0_dqs to first data invalid delay (slew > 1 v/ns) 0.48 ns t dss dmc0_dqs falling edge to clock setup time 0.2 t ck t dsh dmc0_dqs falling edge hold time from dmc0_ck 0.2 t ck t dqsh dmc0_dqs input high pulse width 0.4 t ck t dqsl dmc0_dqs input low pulse width 0.4 t ck t wpre write preamble 0.25 t ck t wpst write postamble 0.4 t ck t ipw address and control output pulse width 2.3 ns t dipw dmc0_dq and dmc0_dm output pulse width 1.8 ns figure 24. mobile ddr sdram controller output ac timing dmc0_ck dmc0_dqs0 - 1 dmc0_dq0 - 15/ dmc0_dqm0 - 1 t dqss t dsh t dss t dqsl t dqsh t wpst t wpre t ds t dh t dipw control write cmd dn dn+1 dn+2 dn+3 note: control = dmc0_cs0 , dmc0_cke, dmc0_ras, dmc0_cas , and dmc0_we. address = dmc0_a00 - 13, and dmc0_ba0 - 1. t dipw t ipw
rev. 0 | page 72 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 enhanced parallel peripheral interface timing table 42 and figure 25 on page 72 , figure 27 on page 74 , figure 26 on page 73 , and figure 28 on page 74 describe enhanced parallel peripheral in terface timing operations. table 42. enhanced parallel periph eral interfaceinternal clock v dd_ext 1.8 v nominal v dd_ext 3.3 v nominal parameter min max min max unit timing requirements t sfspi external frame sync setup before eppi_ clk 7.9 6.5 ns t hfspi external frame sync hold after eppi_clk 0 0 ns t sdrpi receive data setup before eppi_clk 7.9 6.5 ns t hdrpi receive data hold after eppi_clk 0 0 ns switching characteristics t pclkw eppi_clk width for data transmit, fs external data/fs transmit 1 [0.5 t sclk0 C 1.5] or [4.5] [0.5 t sclk0 C 1.5] or [4.5] ns eppi_clk width for data transmit, fs internal data/fs receive 1 [0.5 t sclk0 C 1.5] or [6.5] [0.5 t sclk0 C 1.5] or [6.5] ns t pclk eppi_clk period for data receive, fs external data/fs transmit 1 [t sclk0 C 1.5] or [12] [t sclk0 C 1.5] or [12] ns eppi_clk period for data receive, fs internal data/fs receive 1 [t sclk0 C 1.5] or [16] [t sclk0 C 1.5] or [16] ns t dfspi internal frame sync delay after eppi_clk 3.5 3.5 ns t hofspi internal frame sync hold after eppi_clk C0.5 C0.5 ns t ddtpi transmit data delay after eppi_clk 3.5 3.5 ns t hdtpi transmit data hold after eppi_clk C0.5 C0.5 ns t sfs3ge external fs3 input setup before eppi_clk fall edge in clock gating mode 15.4 14 ns 1 whichever is greater. figure 25. ppi gp receive mode with internal frame sync timing t hdrpi t sdrpi t hofspi frame sync driven data sampled t dfspi t pclk t pclkw eppi_d00 - 23 eppi_clk eppi_fs1/2
rev. 0 | page 73 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 figure 26. ppi gp transmit mode with internal frame sync timing t hofspi frame sync driven data driven t dfspi t ddtpi t hdtpi t pclk t pclkw data driven eppi_d00 - 23 eppi_clk eppi_fs1/2
rev. 0 | page 74 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 table 43. enhanced parallel periph eral interfaceexternal clock v dd_ext 1.8 v nominal v dd_ext 3.3 v nominal parameter min max min max unit timing requirements t pclkw eppi_clk width for data transmit, fs external data/fs receive 1 [0.5 t sclk0 C 0.5] or [5.5] [0.5 t sclk0 C 0.5] or [5.5] ns eppi_clk width for data transmit, fs internal data/fs transmit 1 [0.5 t sclk0 C 1] or [7.5] [0.5 t sclk0 C 1] or [7.5] ns t pclk eppi_clk period for data receive, fs external data/fs receive 1 [t sclk0 C 1] or [12] [t sclk0 C 1] or [12] ns eppi_clk period for data receive, fs internal data/fs transmit 1 [t sclk0 C 1] or [17] [t sclk0 C 1] or [17] ns t sfspe external frame sync setup before eppi_clk 2 2 ns t hfspe external frame sync hold after eppi_clk 3.7 3.7 ns t sdrpe receive data setup before eppi_clk 2 2 ns t hdrpe receive data hold after eppi_clk 3.7 3.7 ns switching characteristics t dfspe internal frame sync delay after eppi_clk 20.1 15.3 ns t hofspe internal frame sync hold after eppi_clk 2.4 2.4 ns t ddtpe transmit data delay after eppi_clk 20.1 15.3 ns t hdtpe transmit data hold after eppi_clk 2.4 2.4 ns 1 whichever is greater. figure 27. ppi gp receive mode with external frame sync timing figure 28. ppi gp transmit mode with external frame sync timing t pclk t sfspe data sampled / frame sync sampled data sampled / frame sync sampled eppi_d00 - 23 eppi_clk eppi_fs1/2 t hfspe t hdrpe t sdrpe t pclkw t hdtpe t sfspe data driven / frame sync sampled t hfspe t ddtpe t pclk t pclkw eppi_d00 - 23 eppi_clk eppi_fs1/2
rev. 0 | page 75 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 link ports calculation of link receiver data setup and hold relative to link clock is required to determin e the maximum allowable skew that can be introduced in the transmission path length differ- ence between lp_dx (data) and lp_clk. setup skew is the maximum delay that can be introduced in lp_dx relative to lp_clk: ? (setup skew = t lclktwh min C t dldch C t sldcl ). hold skew is the maximum delay that can be intr oduced in lp_clk relative to lp_dx: (hold skew = t lclktwl min C t hldch C t hldcl ). table 44. link portsreceive v dd_ext 1.8 v nominal/3.3 v nominal parameter min max unit timing requirements t sldcl data setup before lp_clk low 2 ns t hldcl data hold after lp_clk low 3 ns t lclkiw lp_clk period 1 [t sclk0 C 1] or [12] ns t lclkrwl lp_clk width low 1 [0.5 t sclk0 C 0.5] or [5.5] ns t lclkrwh lp_clk width high 1 [0.5 t sclk0 C 0.5] or [5.5] ns switching characteristic t dlalc lp_ack low delay after lp_clk low 2 1.5 t sclk0 + 4 2.5 t sclk0 + 12 ns 1 whichever is greater. 2 lp_ack goes low with t dlalc relative to rise of lp_clk after firs t byte, but does not go low if the receiv er's link buffer is not about to fill. figure 29. link portsreceive lp_d7C0 lp_clk lp_ack (out) t hldcl t sldcl in t lclkrwh t lclkrwl t lclkiw t dlalc
rev. 0 | page 76 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 table 45. link portstransmit v dd_ext 1.8 v nominal/3.3 v nominal parameter min max unit timing requirements t slach lp_ack setup before lp_clk low 2 t sclk0 + 10 ns t hlach lp_ack hold after lp_clk low 0 ns switching characteristics t dldch data delay after lp_clk high 2.5 ns t hldch data hold after lp_clk high C1 ns t lclktwl lp_clk width low 0.4 t lclk 0.6 t lclk ns t lclktwh lp_clk width high 0.4 t lclk 0.6 t lclk ns t dlaclk lp_clk low delay after lp_ack high t sclk0 + 4 (2 t sclk0 ) + t lclk + 10 ns figure 30. link portstransmit lp_clk lp_dx (data) lp_ack (in) out t dldch t hldch t slach t hlach t dlaclk t lclktwh t lclktwl last byte transmitted first byte transmitted 1 notes the t slach and t hlach specifications apply only to the lp_ack falling edge. if these specifications are met, lp_clk would extend and the dotted lp_clk falling edge would not occur as shown. the position of the dotted falling edge can be calculated using the t lclktwh specification. t lclktwh min should be used for t slach and t lclktwh max for t hlach .
rev. 0 | page 77 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 serial ports to determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) serial clock ? (spt_clk) width. in figure 31 either the rising edge or the fall- ing edge of spt_clk (external or internal) can be used as the active sampling edge. table 46. serial portsexternal clock v dd_ext 1.8 v nominal v dd_ext 3.3 v nominal parameter min max min max unit timing requirements t sfse frame sync setup before spt_clk ? (externally generated frame sync in either transmit or receive mode) 1 22 n s t hfse frame sync hold after spt_clk ? (externally generated frame sync in either transmit or receive mode) 1 2.7 2.7 ns t sdre receive data setup before receive spt_clk 1 22 n s t hdre receive data hold after spt_clk 1 2.7 2.7 ns t sclkw spt_clk width for external spt_clk data/fs receive 2 [0.5 t sclk1 C 0.5] or [5.5] [0.5 t sclk1 C 0.5] or [5.5] ns spt_clk width for external spt_clk data/fs transmit 2 [0.5 t sclk1 C 0.5] or [8] [0.5 t sclk1 C 0.5] or [8] ns t sptclk spt_clk period for external spt_clk data/fs receive 2 [t sclk1 C 1] or [12] [t sclk1 C 1] or [12] ns spt_clk period for external spt_clk data/fs transmit 2 [t sclk1 C 1] or [17] [t sclk1 C 1] or [17] ns switching characteristics t dfse frame sync delay after spt_clk ? (internally generated frame sync in either transmit or receive mode) 3 19.3 14.5 ns t hofse frame sync hold after spt_clk ? (internally generated frame sync in either transmit or receive mode) 3 22 n s t ddte transmit data delay after transmit spt_clk 3 18.8 14 ns t hdte transmit data hold after transmit spt_clk 3 22 n s 1 referenced to sample edge. 2 whichever is greater. 3 referenced to drive edge.
rev. 0 | page 78 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 table 47. serial portsinternal clock v dd_ext 1.8 v nominal v dd_ext 3.3 v nominal parameter min max min max unit timing requirements t sfsi frame sync setup before spt_clk ? (externally generated frame sync in either transmit or receive mode) 1 16.8 12 ? ns t hfsi frame sync hold after spt_clk ? (externally generated frame sync in either transmit or receive mode) 1 0C 0 . 5 ? ns t sdri receive data setup before spt_clk 1 4.8 3.4 ns t hdri receive data hold after spt_clk 1 1.5 1.5 ns switching characteristics t dfsi frame sync delay after spt_clk (internally generated frame sync in transmit or receive mode) 2 3.5 3.5 ns t hofsi frame sync hold after spt_clk (internally generated frame sync in transmit or receive mode) 2 C1.0 C1.0 ns t ddti transmit data delay after spt_clk 2 3.5 3.5 ns t hdti transmit data hold after spt_clk 2 C1.25 C1.25 ns t sclkiw spt_clk width for internal spt_clk data/fs transmit 3 [0.5 t sclk1 C 1.5] or [4.5] [0.5 t sclk1 C 1.5] or [4.5] ns spt_clk width for internal spt_clk data/fs receive [0.5 t sclk1 C 1.5] or [6.5] [0.5 t sclk1 C 1.5] or [6.5] ns t sptclk spt_clk period for internal spt_clk data/fs transmit 3 [t sclk1 C 1.5] or [12] [t sclk1 C 1.5] or [12] ns t sptclk spt_clk period for internal spt_clk data/fs receive 3 [t sclk1 C 1.5] or [16] [t sclk1 C 1.5] or [16] ns 1 referenced to the sample edge. 2 referenced to drive edge. 3 whichever is greater.
rev. 0 | page 79 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 figure 31. serial ports drive edge sample edge spt_a/bdx (data channel a/b) spt_a/bfs (frame sync) spt_a/bclk (sport clock) t hofsi t hfsi t hdri data receiveinternal clock drive edge sample edge t hfsi t ddti data transmitinternal clock drive edge sample edge t hofse t hofsi t hdti t hfse t hdte t ddte data transmitexternal clock drive edge sample edge t hofse t hfse t hdre data receiveexternal clock t sclkiw t dfsi t sfsi t sdri t sclkw t dfse t sfse t sdre t dfse t sfse t sfsi t dfsi t sclkiw t sclkw spt_a/bdx (data channel a/b) spt_a/bfs (frame sync) spt_a/bclk (sport clock) spt_a/bdx (data channel a/b) spt_a/bfs (frame sync) spt_a/bclk (sport clock) spt_a/bdx (data channel a/b) spt_a/bfs (frame sync) spt_a/bclk (sport clock)
rev. 0 | page 80 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 table 48. serial portsenable and three-state v dd_ext 1.8 v nominal v dd_ext 3.3 v nominal parameter min max min max unit switching characteristics t ddten data enable from external transmit spt_clk 1 11n s t ddtte data disable from external transmit spt_clk 1 18.8 14 ns t ddtin data enable from internal transmit spt_clk 1 C1 C1 ns t ddtti data disable from internal transmit spt_clk 1 2.8 2.8 ns 1 referenced to drive edge. figure 32. serial portsenable and three-state drive edge drive edge t ddtin t ddten t ddtte spt_clk (sport clock internal) spt_a/bdx (data channel a/b) spt_clk (sport clock external) spt_a/bdx (data channel a/b) drive edge drive edge t ddtti
rev. 0 | page 81 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 the spt_tdv output signal becomes active in sport multi- channel mode. during transmit slots (enabled with active channel selection registers) th e spt_tdv is asserted for com- munication with external devices. table 49. serial portstd v (transmit data valid) v dd_ext 1.8 v nominal v dd_ext 3.3 v nominal parameter min max min max unit switching characteristics t drdven data-valid enable delay from drive edge of external clock 1 22n s t dfdven data-valid disable delay from drive edge of external clock 1 18.8 14 ns t drdvin data-valid enable delay from drive edge of internal clock 1 C1 C1 ns t dfdvin data-valid disable delay from drive edge of internal clock 1 3.5 3.5 ns 1 referenced to drive edge. figure 33. serial portstransmit data valid internal and external clock drive edge drive edge spt_clk (sport clock external) t drdven t dfdven drive edge drive edge spt_clk (sport clock internal) t drdvin t dfdvin spt_a/btdv spt_a/btdv
rev. 0 | page 82 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 table 50. serial portsexternal late frame sync v dd_ext 1.8 v nominal v dd_ext 3.3 v nominal parameter min max min max unit switching characteristics t ddtlfse data delay from late external transmit frame sync or external receive frame sync with mce = 1, mfd = 0 1 18.8 14 ns ? t ddtenfs data enable for mce = 1, mfd = 0 1 0.5 0.5 ns 1 the t ddtlfse and t ddtenfs parameters apply to left-justi fied as well as standard seri al mode, and mce = 1, mfd = 0. figure 34. external late frame sync drive sample 2nd bit 1st bit drive t ddte/i t hdte/i t ddtlfse t ddtenfs t sfse/i t hfse/i spt_a/bdx (data channel a/b) spt_a/bfs (frame sync) spt_a/bclk (sport clock)
rev. 0 | page 83 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 serial peripheral interface (spi) portmaster timing table 51 and figure 35 describe spi port master operations. note that: ? in dual mode data transmit th e spi_miso signal is also an output. ? in quad mode data transmit the spi_miso, spi_d2, and spi_d3 signals are also outputs. ? in dual mode data receive the spi_mosi signal is also an input. ? in quad mode data receive the spi_mosi, spi_d2, and spi_d3 signals are also inputs. table 51. serial peripheral interface (spi) portmaster timing parameter v dd_ext 1.8 v/3.3 v nominal min max unit timing requirements t sspidm data input valid to spi_clk edge (data input setup) 3.2 ns t hspidm spi_clk sampling edge to data input invalid 1.2 ns switching characteristics t sdscim spi_sel low to first spi_clk edge 1 [0.5 t sclk1 C 2] or [5] ns t spichm spi_clk high period for data transmit 1 [0.5 t sclk1 C 1] or [5] ns spi_clk high period for data receive 1 [0.5 t sclk1 C 1] or [5] ns t spiclm spi_clk low period for data transmit 1 [0.5 t sclk1 C 1] or [5] ns spi_clk low period for data receive 1 [0.5 t sclk1 C 1] or [5] ns t spiclk spi_clk period for data transmit 1 [t sclk1 C 1] or [12] ns spi_clk period for data receive 1 [t sclk1 C 1] or [13.33] ns t hdsm last spi_clk edge to spi_sel high 2 t sclk1 C 1 n s t spitdm sequential transfer delay 1 [0.5 t sclk1 C 1] or [5] ns t ddspidm spi_clk edge to data out valid (data out delay) 2.6 ns t hdspidm spi_clk edge to data out invalid (data out hold) C1 ns 1 whichever is greater.
rev. 0 | page 84 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 figure 35. serial peripheral interface (spi) portmaster timing t sdscim t spiclk t hdsm t spitdm t spiclm t spichm t hdspidm t hspidm t sspidm spi_sel (output) spi_clk (output) data outputs (spi_mosi) cpha = 1 cpha = 0 t ddspidm t hspidm t sspidm t hdspidm t ddspidm data inputs (spi_miso) data outputs (spi_mosi) data inputs (spi_miso)
rev. 0 | page 85 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 serial peripheral interface (spi) portslave timing table 52 and figure 36 describe spi port slave operations. note that: ? in dual mode data transmit th e spi_mosi signal is also an output. ? in quad mode data transmit the spi_mosi, spi_d2, and spi_d3 signals are also outputs. ? in dual mode data receive the spi_miso signal is also an input. ? in quad mode data receive the spi_miso, spi_d2, and spi_d3 signals are also inputs. table 52. serial peripheral interface (spi) portslave timing parameter v dd_ext 1.8 v/3.3 v nominal min max unit timing requirements t spichs spi_clk high period for data transmit 1 [0.5 t sclk1 C 1.5] or [7.0] ns spi_clk high period for data receive 1 [0.5 t sclk1 C 1.5] or [4.5] ns t spicls spi_clk low period for data transmit 1 [0.5 t sclk1 C 1.5] or [7.0] ns spi_clk low period for data receive 1 [0.5 t sclk1 C 1.5] or [4.5] ns t spiclk spi_clk period for data transmit 1 [t sclk1 C 1.5] or [17] ns spi_clk period for data receive 1 [t sclk1 C 1.5] or [12] ns t hds last spi_clk edge to spi_ss not asserted 5 ns t spitds sequential transfer delay 0.5 t spiclk C 1.5 ns t sdsci spi_ss assertion to first spi_clk edge 10.5 ns t sspid data input valid to spi_clk edge (data input setup) 2.0 ns t hspid spi_clk sampling edge to data input invalid 1.6 ns switching characteristics t dsoe spi_ss assertion to data out active 0 14 ns t dsdhi spi_ss deassertion to data high impedance 0 12.5 ns t ddspid spi_clk edge to data out valid (data out delay) 14 ns t hdspid spi_clk edge to data out invalid (data out hold) 0 ns 1 whichever is greater.
rev. 0 | page 86 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 figure 36. serial peripheral interface (spi) portslave timing t spiclk t hds t spitds t sdsci t spicls t spichs t dsoe t ddspid t ddspid t dsdhi t hdspid t sspid t dsdhi t hdspid t dsoe t hspid t sspid t ddspid spi_ss (input) spi_clk (input) t hspid data outputs (spi_miso) cpha = 1 cpha = 0 data inputs (spi_mosi) data outputs (spi_miso) data inputs (spi_mosi)
rev. 0 | page 87 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 serial peripheral interface (spi) portspi_rdy slave timing table 53. spi portspi_rdy slave timing v dd_ext 1.8 v/3.3 v nominal parameter min max unit switching characteristics t dspisckrdysr spi_rdy de-assertion from valid input spi_clk edge in slave mode receive 2.5 t sclk1 3.5 t sclk1 + 17.5 ns t dspisckrdyst spi_rdy de-assertion from valid input spi_clk edge in slave mode transmit 3.5 t sclk1 4.5 t sclk1 + 17.5 ns figure 37. spi_rdy de-assertion from valid inpu t spi_clk edge in slave mode receive (fcch = 0) figure 38. spi_rdy de-assertion fr om valid input spi_clk edge in slave mode tran smit (fcch = 1) spi_clk (cpol = 0) spi_clk (cpol = 1) t dspisckrdysr spi_rdy (o) spi_clk (cpol = 0) spi_clk (cpol = 1) cpha = 1 cpha = 0 spi_clk (cpol = 1) spi_clk (cpol = 0) t dspisckrdyst spi_rdy (o) spi_clk (cpol = 1) spi_clk (cpol = 0) cpha = 1 cpha = 0
rev. 0 | page 88 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 serial peripheral interface (spi) portopen drain mode timing in figure 39 and figure 40, the outputs can be spi_mosi spi_ miso, spi_d2, and/or spi_d3 depending on the mode of operation. table 54. spi port odm master mode timing v dd_ext 1.8 v/3.3 v nominal parameter min max unit switching characteristics t hdspiodmm spi_clk edge to high impeda nce from data out valid C1 ns t ddspiodmm spi_clk edge to data out va lid from high impedance 0 6 ns figure 39. odm master table 55. spi portodm slave mode v dd_ext 1.8 v/3.3 v nominal parameter min max unit timing requirements t hdspiodms spi_clk edge to high impeda nce from data out valid 0 ns t ddspiodms spi_clk edge to data out vali d from high impedance 11.5 ns figure 40. odm slave spi_clk (cpol = 0) t hdspiodmm spi_clk (cpol = 1) t ddspiodmm t ddspiodmm t hdspiodmm output (cpha = 1) output (cpha = 0) t hdspiodms t ddspiodms t ddspiodms t hdspiodms spi_clk (cpol = 0) spi_clk (cpol = 1) output (cpha = 1) output (cpha = 0)
rev. 0 | page 89 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 serial peripheral interface (spi) portspi_rdy timing table 56. spi portspi_rdy timing v dd_ext 1.8 v/3.3 v nominal parameter min max unit timing requirements t srdysckm0 minimum setup time for spi_rdy de-assertion in master mode before last spi_clk edge of valid data transfer to ? block subsequent transfer with cpha = 0 (2.5 + 1.5 baud 1 ) t sclk1 + 17.5 ns t srdysckm1 minimum setup time for spi_rdy de-assertion in master mode before last spi_clk edge of valid data transfer to ? block subsequent transfer with cpha = 1 (1.5 baud 1 ) t sclk1 + 17.5 ns switching characteristic t srdysckm time between assertion of spi_rdy by slave and first edge ? of spi_clk for new spi transfer with cpha = 0 and baud = 0 (stop, lead, lag = 0) 3 t sclk1 4 t sclk1 + 17.5 ns time between assertion of spi_rdy by slave and first edge ? of spi_clk for new spi transfer with cpha = 0 and baud 1 (stop, lead, lag = 0) (4 + 1.5 baud 1 ) t sclk1 (5 + 1.5 baud 1 ) t sclk1 + 17.5 ns time between assertion of spi_rdy by slave and first edge ? of spi_clk for new spi transfer with cpha = 1 (stop, lead, ? lag = 0) (3 + 0.5 baud 1 ) t sclk1 (4 + 0.5 baud 1 ) t sclk1 + 17.5 ns 1 baud value set using the spi_clk.baud bits. figure 41. spi_rdy setup befo re spi_clk with cpha = 0 figure 42. spi_rdy setup befo re spi_clk with cpha = 1 spi_clk (cpol = 0) spi_clk (cpol = 1) t srdysckm0 spi_rdy spi_clk (cpol = 0) spi_clk (cpol = 1) t srdysckm1 spi_rdy
rev. 0 | page 90 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 figure 43. spi_clk switching diagram after spi_rdy assertion, cpha = x spi_clk (cpol = 0) spi_clk (cpol = 1) t srdysckm spi_rdy
rev. 0 | page 91 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 general-purpose port timing table 57 and figure 44 describe general-purpose ? port operations. timer cycle timing table 58 and figure 45 describe timer expired operations. the input signal is asynchronous in width capture mode and external clock mode and has an absolute maximum input fre- quency of (f sclk0 /4) mhz. the period value value is the timer period assigned in the tmx_tm rn_per register and can range from 2 to 2 32 C 1. table 57. general-purpose port timing v dd_ext 1.8 v/3.3 v nominal parameter min max unit timing requirement t wfi general-purpose port pin input pulse width 2 t sclk0 ns figure 44. general-purpose port timing gpio input t wfi table 58. timer cycle timing parameter v dd_ext 1.8 v nominal v dd_ext 3.3 v nominal min max min max unit timing requirements t wl timer pulse width input low (measured in sclk0 cycles) 1 2 t sclk0 2 t sclk0 ns t wh timer pulse width input high (measured in sclk0 cycles) 1 2 t sclk0 2 t sclk0 ns switching characteristics t hto timer pulse width output (measured in sclk0 cycles) t sclk0 period value t sclk0 period value t sclk0 period value t sclk0 period value ns 1 the minimum pulse widths apply for tmx signal s in width capture and external clock modes. figure 45. timer cycle timing tmr output tmr input t wh , t wl t hto
rev. 0 | page 92 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 up/down counter/rotary encoder timing pulse width modulator (pwm) timing table 60 and figure 47 describe pwm operations. table 59. up/down counter/rotary encoder timing v dd_ext 1.8 v nominal v dd_ext 3.3 v nominal parameter min max min max unit timing requirement t wcount up/down counter/rotary encoder input pulse width 2 t sclk0 2 t sclk0 ns figure 46. up/down counter/rotary encoder timing cnt_ud cnt_dg cnt_zm t wcount table 60. pwm timing v dd_ext 1.8 v nominal v dd_ext 3.3 v nominal parameter min max min max unit timing requirement t es external sync pulse width 2 t sclk0 ns switching characteristics t dodis output inactive (off) after trip input 1 15 ns t doe output delay after external sync 1, 2 2 t sclk0 + 5.5 5 t sclk0 + 14 ns 1 pwm outputs are: pwmx_ah, pwmx_al, pwmx_bh, pwmx_bl, pwmx_ch, and pwmx_cl. 2 when the external sync signal is synchronou s to the peripheral clock, it takes fewer clock cycles for the output to appear comp ared to when the external sync signal is asynchronous to the peripheral cloc k. for more information, see the adsp-bf60x blackfin proc essor hardware reference . figure 47. pwm timing pwm_trip pwm_sync (as input) t es t doe output t dodis
rev. 0 | page 93 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 adc controller module (acm) timing table 61 and figure 48 describe acm operations. note that the acm clock (acmx_clk) frequency in mhz is set by the following equation where ckdiv is a field in the acm_tc0 register and ranges from 1 to 255. setup cycles (sc) in table 61 is also a field in the acm_tc0 register and ranges from 0 to 4095. hold cycles (h c) is a field in the acm_tc1 register that ranges from 0 to 15. f aclk f sclk1 ckdiv 1 + -------------------------- - = t aclk 1 f aclk ----------------- = table 61. acm timing v dd_ext 1.8 v/3.3 v nominal parameter min max unit timing requirements t sdr sport drxpri/drxsec setup before acmx_clk 3 ns t hdr sport drxpri/drxsec hold after acmx_clk 1.5 ns switching characteristics t sctlcs acm controls (acmx_a[4:0]) setup before assertion of cs (sc + 1) t sclk1 C 3 ns t hctlcs acm control (acmx_a[4:0]) hold after de-assertion of cs hc t aclk + 0.1 ns t aclkw acm clock pulse width (t sclk1 /2) (clkdiv + 1) C 1.5 ns t aclk acm clock period 1 [t sclk1 (ckdiv + 1)] or [16] ns t hcsaclk cs hold to acmx_clk edge C0.1 ns t scsaclk cs setup to acmx_clk edge t aclk C 3.5 ns 1 whichever is greater. figure 48. acm timing cs cspol 10 scsaclk acm controls drxpri drxsec aclk sctlcs sdr hdr acm_clk clkpol 10 hcsaclk hctlcs
rev. 0 | page 94 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 universal asynchronous receiver-transmitter ? (uart) portsreceive and transmit timing the uart ports receive and tran smit operations are described in the adsp-bf60x hardware reference manual . can interface the can interface timing is described in the adsp-bf60x hardware reference manual . universal serial bus (usb) on-the-goreceive and transmit timing table 62 describes the usb on-the-go receive and transmit operations. table 62. usb on-the-goreceive and transmit timing parameter v dd_usb 3.3 v nominal min max unit timing requirements f usbs usb_xi frequency 48 48 mhz fs usb usb_xi clock frequency stability C50 +50 ppm
rev. 0 | page 95 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 rsi controller timing table 63 and figure 49 describe rsi controller timing. table 63. rsi controller timing v dd_ext 1.8 v nominal v dd_ext 3.3 v nominal parameter min max min max unit timing requirements t isu input setup time 11 9.6 ns t ih input hold time 2 2 ns switching characteristics f pp clock frequency data transfer mode 1 41.67 41.67 mhz t wl clock low time 8 8 ns t wh clock high time 8 8 ns t tlh clock rise time 3 3 ns t thl clock fall time 3 3 ns t odly output delay time during data transfer mode 2.5 2.5 ns t oh output hold time C1 C1 ns 1 t pp = 1/f pp figure 49. rsi controller timing rsi_clk input output t isu notes: 1 input includes rsi_dx and rsi_cmd signals. 2 output includes rsi_dx and rsi_cmd signals. t thl t tlh t wl t wh t pp t ih t odly t oh v oh (min) v ol (max)
rev. 0 | page 96 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 10/100 ethernet mac controller timing table 64 through table 66 and figure 50 through figure 52 describe the 10/100 ethernet mac cont roller operations. table 64. 10/100 ethernet mac contro ller timing: rmii receive signal parameter 1 v dd_ext 1.8 v/3.3 v nominal min max unit timing requirements t refclkf ethx_refclk frequency (f sclk0 = sclk0 frequency) none 50 + 1% mhz t refclkw ethx_refclk width (t refclk = ethx_refclk period) t refclk 35% t refclk 65% ns t refclkis rx input valid to rmii ethx_refclk rising edge (data in setup) 4 ns t refclkih rmii ethx_refclk rising edge to rx input invalid (data in hold) 2.2 ns 1 rmii inputs synchronous to rmii ref_clk are erxd1C0, rmii crs_dv, and erxer. figure 50. 10/100 ethernet mac controller timing: rmii receive signal table 65. 10/100 ethernet mac controll er timing: rmii transmit signal parameter 1 v dd_ext 1.8 v/3.3 v nominal min max unit switching characteristics t refclkov rmii ethx_refclk rising edge to transmit output valid (data out valid) 14 ns t refclkoh rmii ethx_refclk rising edge to transmit output invalid (data out hold) 2 ns 1 rmii outputs synchronous to rmii ref_clk are etxd1C0. figure 51. 10/100 ethernet mac controller timing: rmii transmit signal t refclkis t refclkih ethx_rxd1C0 ethx_crs ethx_rxerr rmii_ref_clk t refclkw t refclk t refclkov t refclkoh rmii_ref_clk ethx_txd1C0 ethx_txen t refclk
rev. 0 | page 97 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 table 66. 10/100 ethernet mac controller timing: rmii station management parameter 1 v dd_ext 1.8 v/3.3 v nominal min max unit timing requirements t mdios ethx_mdio input valid to ethx_mdc rising edge (setup) 14 ns t mdcih ethx_mdc rising edge to ethx _mdio input invalid (hold) 0 ns switching characteristics t mdcov ethx_mdc falling edge to ethx_mdio output valid t sclk0 + 5 ns t mdcoh ethx_mdc falling edge to ethx _mdio output invalid (hold) t sclk0 C1 ns 1 ethx_mdc/ethx_mdio is a 2-wire se rial bidirectional port for cont rolling one or more external phys. ethx_mdc is an output clock whose minimum period is programmable as a multiple of the system clock sclk0. ethx_mdio is a bid irectional data line. figure 52. 10/100 ethernet mac contro ller timing: rmii station management ethx_mdio (input) ethx_mdio (output) ethx_mdc (output) t mdios t mdcoh t mdcih t mdcov
rev. 0 | page 98 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 jtag test and emulation port timing table 67 and figure 53 describe jtag port operations. table 67. jtag port timing parameter v dd_ext 1.8 v nominal v dd_ext 3.3 v nominal min max min max unit timing requirements t tck jtg_tck period 20 20 ns t stap jtg_tdi, jtg_tms setup before jtg_tck high 4 4 ns t htap jtg_tdi, jtg_tms hold after jtg_tck high 4 4 ns t ssys system inputs setup before jtg_tck high 1 12 12 ns t hsys system inputs hold after jtg_tck high 1 5 5 ns t trstw jtg_trst pulse width (measured in jtg_tck cycles) 2 44t c k switching characteristics t dtdo jtg_tdo delay from jtg_tck low 18 13.5 ns t dsys system outputs delay after jtg_tck low 3 22 17 ns 1 system inputs = dmc0_dq0 0C15, dmc0_ldqs, dmc0_ldqs , dmc0_udqs, dmc0_udqs , pa_15C0, pb_15C0, pc_15C0, pd_15C0, pe_15C0, pf_15C0, pg_15C0, smc0_ardy_norwt, smc0_br , smc0_d15C0, sys_bmode0C2, sys_hwrst , sys_fault, sys_fault , sys_nmi_resout , sys_pwrgd, twi0_scl, twi0_ sda, twi1_scl, twi1_sda. 2 50 mhz maximum. 3 system outputs = dmc0_a00 C13, dmc0_ba0C2, dmc0_cas , dmc0_ck, dmc0_ck , dmc0_cke, dmc0_cs0 , dmc0_dq00C15, dmc0_ldm, dmc0_ldqs, dmc0_ldqs , dmc0_odt, dmc0_ras , dmc0_udm, dmc0_udqs, dmc0_udqs , dmc0_we , jtg_emu , pa_15C0, pb_15C0, pc_15C0, pd_15C0, pe_15C0, pf_ 15C0, pg_15C0, smc0_ams0 , smc0_aoe _nordv, smc0_are , smc0_awe , smc0_a01, smc0_a02, smc0_d15C0, sys_clkout, sys_fault, sys_fault , sys_nmi_resout , twi0_scl, twi0_sda, twi1_scl, twi1_sda. figure 53. jtag port timing jtg_tck jtg_tms jtg_tdi jtg_tdo system inputs system outputs t tck t stap t htap t dtdo t ssys t hsys t dsys
rev. 0 | page 99 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 output drive currents figure 54 through figure 59 show typical current-voltage char- acteristics for the output driver s of the adsp-bf60x blackfin processors. the curves represent the current drive capability of the output drivers as a function of output voltage. figure 54. driver type a current (1.8 v v dd_ext ) figure 55. driver type a current (3.3 v v dd_ext ) 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 40 C 20 v ol v oh v dd_ext = 1.9v @ C 40 c v dd_ext = 1.8v @ 25 c C 40 20 v dd_ext = 1.7v @ 125 c 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 60 40 C 60 C 20 v ol v oh 4.0 v dd_ext = 3.465v @ C 40 c v dd_ext = 3.30v @ 25 c C 40 C 80 20 80 v dd_ext = 3.135v @ 105 c figure 56. driver type b current (1.8 v v dd_dmc ) figure 57. driver type c current (1.8 v v dd_dmc ) 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 100 60 40 C 60 C 20 v ol v oh v dd_dmc = 1.9v @ C 40 c v dd_dmc = 1.8v @ 25 c C 40 C 80 20 80 v dd_dmc = 1.7v @ 125 c 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 100 60 40 C 60 C 20 v ol v oh C 40 C 80 20 80 v dd_dmc = 1.9v @ C 40 c v dd_dmc = 1.8v @ 25 c v dd_dmc = 1.7v @ 125 c
rev. 0 | page 100 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 capacitive loading output delays and holds are based on standard capacitive loads of an average of 6 pf on all pins (see figure 60 ). v load is equal to (v dd_ext )/2. the graphs of figure 61 through figure 63 show how output rise and fall times vary with ca pacitance. the delay and hold specifications given should be derated by a factor derived from these figures. the graphs in thes e figures may not be linear out- side the ranges shown. figure 58. driver type d current (1.8 v v dd_ext ) figure 59. driver type d current (3.3 v v dd_ext ) C 10 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 0 C 20 v ol v dd_ext = 1.9v @ C 40 c v dd_ext = 1.8v @ 25 c C 5 v dd_ext = 1.7v @ 125 c C 15 C 40 source current (ma) source voltage (v) 0 1.0 2.0 3.0 4.0 0 C 60 v ol v dd_ext = 3.465v @ C 40 c v dd_ext = 3.30v @ 25 c C 20 v dd_ext = 3.135v @ 125 c figure 60. equivalent device loading for ac measurements (includes all fixtures) figure 61. driver type a typical rise and fall times (10%-90%) vs. load capacitance (v dd_ext = 1.8 v) t1 zo = 50:(impedance) td = 4.04 1.18 ns 2pf tester pin electronics 50 : 0.5pf 70 : 400 : 45 : 4pf notes: the worst case transmission line delay is shown and can be used for the output timing analysis to refelect the transmission line effect and must be considered. the transmission line (td) is for load only and does not affect the data sheet timing specifications. analog devices recommends using the ibis model timing for a given system requirement. if necessary, a system may incorporate external drivers to compensate for any timing differences. v load dut output 50 : load capacitance (pf) 12 0 14 8 4 2 6 rise and fall times (ns) 10 0 250 200 50 100 150 16 t rise t fall t fall = 1.8v @ 25 c t rise = 1.8v @ 25 c
rev. 0 | page 101 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 environmental conditions to determine the junction te mperature on the application printed circuit board use: ? ? where: t j = junction temperature (c) t case = case temperature (c) me asured by customer at top center of package. ? jt = from table 68 p d = power dissipation (see total internal power dissipation on page 56 for the method to calculate p d ) values of ? ja are provided for packag e comparison and printed circuit board design considerations. ? ja can be used for a first order approximation of t j by the equation: ? ? where: t a = ambient temperature (c) values of ? jc are provided for packag e comparison and printed circuit board design considerations when an external heat sink is required. in table 68 , airflow measurements comply with jedec stan- dards jesd51-2 and jesd51-6. the junction-to-case measurement complies with mil-std-883 (method 1012.1). all measurements use a 2s2p jedec test board. figure 62. driver type a typical rise and fall times (10%-90%) vs. load capacitance (v dd_ext = 3.3 v) figure 63. driver type b & c typical ri se and fall times (10%-90%) vs. load capacitance (v dd_dmc = 1.8 v) load capacitance (pf) 12 0 14 8 4 2 6 rise and fall times (ns) 10 0 250 200 50 100 150 16 t rise t fall t fall = 3.3v @ 25 c t rise = 3.3v @ 25 c load capacitance (pf) 1.2 0 1.4 0.8 0.4 0.2 0.6 rise and fall times (ns) 1.0 02 5 20 51015 t fall = 1.8v @ 25 c t rise = 1.8v @ 25 c 35 30 t rise ds = 10 t fall ds = 10 t rise ds = 00 t fall ds = 00 table 68. thermal characteristics parameter condition typical unit ? ja 0 linear m/s air flow 16.7 c/w ? jma 1 linear m/s air flow 14.6 c/w ? jma 2 linear m/s air flow 13.9 c/w ? jc 4.41 c/w ? jt 0 linear m/s air flow 0.11 c/w ? jt 1 linear m/s air flow 0.24 c/w ? jt 2 linear m/s air flow 0.25 c/w t j t case ? jt p d ? ?? += t j t a ? ja p d ? ?? +=
rev. 0 | page 102 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 thermal diode the processor incorporates a th ermal diode to monitor the die temperature. the thermal diode is a grounded collector, pnp bipolar junction tran sistor (bjt). the sys_tda ball is con- nected to the emitter and the sy s_tdk ball is connected to the base of the tran sistor. these balls can be used by an external temperature sensor (such as the adm 1021a or the lm86 or others) to read the die temperature of the chip. the technique used by the extern al temperature sensor is to measure the change in v be when the thermal diode is operated at two different currents. this is shown in the following equation: ? ? where: n q = multiplication factor clos e to 1, depending on process variations k = boltzmanns constant t = temperature (kelvin) q = charge of the electron n = ratio of the two currents the two currents are usually in the range of 10 micro amperes to 300 micro amperes for the common temperature sensor chips available. table 69 contains the thermal diod e specifications using the transistor model. note that me asured ideality factor already takes into effect variations in beta (). ? v be n q kt q ------ in(n) ?? = table 69. thermal diode parameterstransistor model symbol parameter min typ max unit i fw 1 forward bias current 10 300 ? a i e emitter current 10 300 ? a n q 2, 3 transistor ideality 1.006 r t 2, 4 series resistance 2.8 ? 1 analog devices does not reco mmend operation of the the rmal diode under reverse bias. 2 not 100% tested. specified by design characterization. 3 the ideality factor, n q , represents the deviation from ideal diode behavior as exemplified by the diode equation: i c = i s (exp(qv be /n q ktC 1), where i s = saturation current, ? q = electrical charge, v be = voltage across the diode, k = boltzmann co nstant, and t = absolute temperature (kelvin). 4 the series resistance (r t ) can be used for more acc urate readings as needed.
rev. 0 | page 103 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 adsp-bf60x 349-ball csp_bga ball assignments the 349-ball csp_bga ball assignme nt (numerical by ball number) table lists the csp_bga package by ball number for the adsp-bf609. the 349-ball csp_bga ball assignme nt (alphabetical by pin name) table lists the csp_bga package by signal. 349-ball csp_bga ball assignment (numerical by ball number) ball no. pin name a01 gnd a02 usb0_dm a03 usb0_dp a04 pb_10 a05 pb_07 a06 pa_14 a07 pa_12 a08 pa_10 a09 pa_08 a10 pa_06 a11 pa_04 a12 pa_02 a13 pa_00 a14 smc0_a01 a15 smc0_d00 a16 smc0_ams0 a17 smc0_d03 a18 smc0_d04 a19 smc0_d07 a20 smc0_d10 a21 smc0_awe a22 gnd b01 usb0_vbus b02 gnd b03 usb0_id b04 pb_11 b05 pb_08 b06 pa_15 b07 pa_13 b08 pa_11 b09 pa_09 b10 pa_07 b11 pa_05 b12 pa_03 b13 pa_01 b14 smc0_a02 b15 smc0_d01 b16 smc0_d15 b17 smc0_d09 b18 smc0_d02 b19 smc0_d13 b20 smc0_d05 b21 gnd b22 smc0_aoe _nordv c01 usb0_clkin c02 usb0_vbc c03 gnd c04 pb_12 c05 pb_09 c06 pb_06 c07 pb_05 c08 pb_04 c09 pb_03 c10 pb_02 c11 pb_01 c12 pb_00 c13 smc0_br c14 smc0_d06 c15 smc0_d12 c16 smc0_are c17 smc0_d08 c18 smc0_d11 c19 smc0_d14 c20 gnd c21 twi1_scl c22 twi0_scl d01 jtg_tdi d02 jtg_tdo d03 jtg_tck d11 v dd_ext d12 gnd d20 smc0_ardy_norwt d21 twi1_sda d22 twi0_sda e01 jtg_trst e02 jtg_emu e03 jtg_tms e05 v dd_usb e20 dmc0_cas e21 dmc0_dq10 ball no. pin name e22 dmc0_dq13 f01 sys_fault f02 sys_fault f03 sys_nmi_resout f06 v dd_ext f07 v dd_int f08 v dd_int f09 v dd_int f10 v dd_int f11 v dd_ext f12 v dd_ext f13 v dd_int f14 v dd_int f15 v dd_int f16 v dd_int f17 v dd_dmc f20 dmc0_cs0 f21 dmc0_dq15 f22 dmc0_dq08 g01 gnd g02 sys_hwrst g03 sys_bmode2 g06 v dd_ext g07 v dd_ext g08 v dd_int g09 v dd_int g10 v dd_ext g11 v dd_ext g12 v dd_ext g13 v dd_ext g14 v dd_int g15 v dd_int g16 v dd_dmc g17 v dd_dmc g20 dmc0_udm g21 dmc0_udqs g22 dmc0_udqs h01 sys_clkin h02 sys_xtal h03 sys_bmode1 ball no. pin name h06 v dd_ext h07 v dd_ext h16 v dd_dmc h17 v dd_dmc h20 dmc0_ras h21 dmc0_dq09 h22 dmc0_dq14 j01 gnd j02 sys_pwrgd j03 sys_bmode0 j06 v dd_ext j09 gnd j10 gnd j11 gnd j12 gnd j13 gnd j14 gnd j17 v dd_dmc j20 dmc0_odt j21 dmc0_dq12 j22 dmc0_dq11 k01 pc_00 k02 sys_extwake k03 pb_13 k06 v dd_ext k08 gnd k09 gnd k10 gnd k11 gnd k12 gnd k13 gnd k14 gnd k15 gnd k17 v dd_dmc k20 dmc0_ldm k21 dmc0_ldqs k22 dmc0_ldqs l01 pc_02 l02 pc_01 l03 pb_14 ball no. pin name
rev. 0 | page 104 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 l04 v dd_ext l06 v dd_ext l08 gnd l09 gnd l10 gnd l11 gnd l12 gnd l13 gnd l14 gnd l15 gnd l17 v dd_dmc l19 vref_dmc l20 dmc0_ck l21 dmc0_dq06 l22 dmc0_dq07 m01 pc_04 m02 pc_03 m03 pb_15 m04 gnd m06 v dd_ext m08 gnd m09 gnd m10 gnd m11 gnd m12 gnd m13 gnd m14 gnd m15 gnd m17 v dd_dmc m19 gnd m20 dmc0_ck m21 dmc0_dq00 m22 dmc0_dq01 n01 pc_06 n02 pc_05 n03 sys_clkout n06 v dd_ext n08 gnd n09 gnd n10 gnd n11 gnd n12 gnd n13 gnd n14 gnd n15 gnd n17 v dd_dmc n20 dmc0_we n21 dmc0_dq04 ball no. pin name n22 dmc0_dq03 p01 pc_08 p02 pc_07 p03 pd_06 p06 v dd_ext p09 gnd p10 gnd p11 gnd p12 gnd p13 gnd p14 gnd p17 v dd_dmc p20 dmc0_cke p21 dmc0_dq02 p22 dmc0_dq05 r01 pc_10 r02 pc_09 r03 pd_07 r06 v dd_ext r07 v dd_ext r16 v dd_dmc r17 v dd_dmc r20 dmc0_ba2 r21 dmc0_ba0 r22 dmc0_a10 t01 pc_12 t02 pc_11 t03 pd_08 t06 v dd_ext t07 v dd_ext t08 v dd_int t09 v dd_int t10 v dd_ext t11 v dd_ext t12 v dd_ext t13 v dd_ext t14 v dd_int t15 v dd_int t16 v dd_dmc t17 v dd_dmc t20 dmc0_a03 t21 dmc0_a07 t22 dmc0_a12 u01 pc_14 u02 pc_13 u03 pd_09 u06 v dd_ext u07 v dd_int ball no. pin name u08 v dd_int u09 v dd_int u10 v dd_int u11 v dd_ext u12 v dd_ext u13 v dd_int u14 v dd_int u15 v dd_int u16 v dd_int u17 v dd_dmc u20 dmc0_a09 u21 dmc0_a05 u22 dmc0_a01 v01 pd_00 v02 pc_15 v03 pd_10 v20 dmc0_ba1 v21 dmc0_a13 v22 dmc0_a11 w01 pd_04 w02 pd_01 w03 pd_12 w11 gnd w12 v dd_td w20 dmc0_a04 w21 dmc0_a06 w22 dmc0_a08 y01 pd_03 y02 pd_02 y03 gnd y04 pd_15 y05 pe_02 y06 pe_05 y07 pe_06 y08 pe_07 y09 pe_08 y10 pe_09 y11 sys_tdk y12 sys_tda y13 pe_12 y14 pe_10 y15 pe_11 y16 pg_09 y17 pg_01 y18 pg_04 y19 pg_11 y20 gnd y21 dmc0_a00 ball no. pin name y22 dmc0_a02 aa01 pd_11 aa02 gnd aa03 pd_13 aa04 pe_00 aa05 pe_03 aa06 pf_14 aa07 pf_12 aa08 pf_10 aa09 pf_08 aa10 pf_06 aa11 pf_04 aa12 pf_02 aa13 pf_00 aa14 pg_00 aa15 pe_15 aa16 pe_14 aa17 pg_05 aa18 pg_08 aa19 pg_07 aa20 pg_13 aa21 gnd aa22 gnd ab01 gnd ab02 pd_05 ab03 pd_14 ab04 pe_01 ab05 pe_04 ab06 pf_15 ab07 pf_13 ab08 pf_11 ab09 pf_09 ab10 pf_07 ab11 pf_05 ab12 pf_03 ab13 pf_01 ab14 pe_13 ab15 pg_03 ab16 pg_06 ab17 pg_02 ab18 pg_12 ab19 pg_14 ab20 pg_15 ab21 pg_10 ab22 gnd ball no. pin name
rev. 0 | page 105 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 349-ball csp_bga ball assignment (alphabetical by pin name) the 349-ball csp_bga ball assignme nt (numerical by ball number) table lists the csp_bga package by ball number for the adsp-bf609. the 349-ball csp_bga ball assignme nt (alphabetical by pin name) table lists the csp_bga package by signal. pin name ball no. dmc0_a00 y21 dmc0_a01 u22 dmc0_a02 y22 dmc0_a03 t20 dmc0_a04 w20 dmc0_a05 u21 dmc0_a06 w21 dmc0_a07 t21 dmc0_a08 w22 dmc0_a09 u20 dmc0_a10 r22 dmc0_a11 v22 dmc0_a12 t22 dmc0_a13 v21 dmc0_ba0 r21 dmc0_ba1 v20 dmc0_ba2 r20 dmc0_cas e20 dmc0_ck m20 dmc0_cke p20 dmc0_ck l20 dmc0_cs0 f20 dmc0_dq00 m21 dmc0_dq01 m22 dmc0_dq02 p21 dmc0_dq03 n22 dmc0_dq04 n21 dmc0_dq05 p22 dmc0_dq06 l21 dmc0_dq07 l22 dmc0_dq08 f22 dmc0_dq09 h21 dmc0_dq10 e21 dmc0_dq11 j22 dmc0_dq12 j21 dmc0_dq13 e22 dmc0_dq14 h22 dmc0_dq15 f21 dmc0_ldm k20 dmc0_ldqs k22 dmc0_ldqs k21 dmc0_odt j20 dmc0_ras h20 dmc0_udm g20 dmc0_udqs g21 dmc0_udqs g22 dmc0_we n20 gnd a01 gnd a22 gnd aa02 gnd aa21 gnd aa22 gnd ab01 gnd ab22 gnd b21 gnd c20 gnd d12 gnd g01 gnd j01 gnd j09 gnd j10 gnd j11 gnd j12 gnd j13 gnd j14 gnd k08 gnd k09 gnd k10 gnd k11 gnd k12 gnd k13 gnd k14 gnd k15 gnd l08 gnd l09 gnd l10 gnd l11 gnd l12 gnd l13 gnd l14 gnd l15 gnd m04 gnd m08 gnd m09 gnd m10 gnd m11 gnd m12 gnd m13 gnd m14 gnd m15 gnd m19 gnd n08 pin name ball no. gnd n09 gnd n10 gnd n11 gnd n12 gnd n13 gnd n14 gnd n15 gnd p09 gnd p10 gnd p11 gnd p12 gnd p13 gnd p14 gnd w11 gnd y03 gnd y20 gnd c03 gnd b02 jtg_emu e02 jtg_tck d03 jtg_tdi d01 jtg_tdo d02 jtg_tms e03 jtg_trst e01 pa_00 a13 pa_01 b13 pa_02 a12 pa_03 b12 pa_04 a11 pa_05 b11 pa_06 a10 pa_07 b10 pa_08 a09 pa_09 b09 pa_10 a08 pa_11 b08 pa_12 a07 pa_13 b07 pa_14 a06 pa_15 b06 pb_00 c12 pb_01 c11 pb_02 c10 pb_03 c09 pb_04 c08 pb_05 c07 pin name ball no. pb_06 c06 pb_07 a05 pb_08 b05 pb_09 c05 pb_10 a04 pb_11 b04 pb_12 c04 pb_13 k03 pb_14 l03 pb_15 m03 pc_00 k01 pc_01 l02 pc_02 l01 pc_03 m02 pc_04 m01 pc_05 n02 pc_06 n01 pc_07 p02 pc_08 p01 pc_09 r02 pc_10 r01 pc_11 t02 pc_12 t01 pc_13 u02 pc_14 u01 pc_15 v02 pd_00 v01 pd_01 w02 pd_02 y02 pd_03 y01 pd_04 w01 pd_05 ab02 pd_06 p03 pd_07 r03 pd_08 t03 pd_09 u03 pd_10 v03 pd_11 aa01 pd_12 w03 pd_13 aa03 pd_14 ab03 pd_15 y04 pe_00 aa04 pe_01 ab04 pe_02 y05 pe_03 aa05 pin name ball no.
rev. 0 | page 106 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 pe_04 ab05 pe_05 y06 pe_06 y07 pe_07 y08 pe_08 y09 pe_09 y10 pe_10 y14 pe_11 y15 pe_12 y13 pe_13 ab14 pe_14 aa16 pe_15 aa15 pf_00 aa13 pf_01 ab13 pf_02 aa12 pf_03 ab12 pf_04 aa11 pf_05 ab11 pf_06 aa10 pf_07 ab10 pf_08 aa09 pf_09 ab09 pf_10 aa08 pf_11 ab08 pf_12 aa07 pf_13 ab07 pf_14 aa06 pf_15 ab06 pg_00 aa14 pg_01 y17 pg_02 ab17 pg_03 ab15 pg_04 y18 pg_05 aa17 pg_06 ab16 pg_07 aa19 pg_08 aa18 pg_09 y16 pg_10 ab21 pg_11 y19 pg_12 ab18 pg_13 aa20 pg_14 ab19 pg_15 ab20 smc0_a01 a14 smc0_a02 b14 smc0_ams0 a16 smc0_aoe _nordv b22 smc0_ardy_norwt d20 smc0_are c16 pin name ball no. smc0_awe a21 smc0_br c13 smc0_d00 a15 smc0_d01 b15 smc0_d02 b18 smc0_d03 a17 smc0_d04 a18 smc0_d05 b20 smc0_d06 c14 smc0_d07 a19 smc0_d08 c17 smc0_d09 b17 smc0_d10 a20 smc0_d11 c18 smc0_d12 c15 smc0_d13 b19 smc0_d14 c19 smc0_d15 b16 sys_bmode0 j03 sys_bmode1 h03 sys_bmode2 g03 sys_clkin h01 sys_clkout n03 sys_extwake k02 sys_fault f02 sys_fault f01 sys_nmi_resout f03 sys_pwrgd j02 sys_hwrst g02 sys_tda y12 sys_tdk y11 sys_xtal h02 twi0_scl c22 twi0_sda d22 twi1_scl c21 twi1_sda d21 usb0_clkin c01 usb0_dm a02 usb0_dp a03 usb0_id b03 usb0_vbc c02 usb0_vbus b01 v dd_dmc f17 v dd_dmc g16 v dd_dmc g17 v dd_dmc h16 v dd_dmc h17 v dd_dmc j17 v dd_dmc k17 v dd_dmc l17 pin name ball no. v dd_dmc m17 v dd_dmc n17 v dd_dmc p17 v dd_dmc r16 v dd_dmc r17 v dd_dmc t16 v dd_dmc t17 v dd_dmc u17 v dd_ext d11 v dd_ext f06 v dd_ext f11 v dd_ext f12 v dd_ext g06 v dd_ext g07 v dd_ext g10 v dd_ext g11 v dd_ext g12 v dd_ext g13 v dd_ext h06 v dd_ext h07 v dd_ext j06 v dd_ext k06 v dd_ext l04 v dd_ext l06 v dd_ext m06 v dd_ext n06 v dd_ext p06 v dd_ext r06 v dd_ext r07 v dd_ext t06 v dd_ext t07 v dd_ext t10 v dd_ext t11 v dd_ext t12 v dd_ext t13 v dd_ext u06 v dd_ext u11 v dd_ext u12 v dd_int f07 v dd_int f08 v dd_int f09 v dd_int f10 v dd_int f13 v dd_int f14 v dd_int f15 v dd_int f16 v dd_int g08 v dd_int g09 v dd_int g14 v dd_int g15 pin name ball no. v dd_int t08 v dd_int t09 v dd_int t14 v dd_int t15 v dd_int u07 v dd_int u08 v dd_int u09 v dd_int u10 v dd_int u13 v dd_int u14 v dd_int u15 v dd_int u16 v dd_td w12 v dd_usb e05 vref_dmc l19 pin name ball no.
rev. 0 | page 107 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 349-ball csp_bga ball configuration figure 64 shows an overview of sign al placement on the 349-ball csp_bga package. figure 64. 349-ball csp_bga ball configuration a1 ball pad corner 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 17 18 19 20 21 22 m b c d e f g h j k l n r t a u v w y aa ab p v dd_int v dd_ext gnd i/o signals d v dd_dmc d d d d d d d d d d d d d d d d u u v dd_usb a1 ball pad corner 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 17 18 19 20 21 22 m b c d e f g h j k l n r t a u v w y aa ab p d d d d d d d d d d d d d d d d u top view bottom view t v dd_td t t
rev. 0 | page 108 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 outline dimensions dimensions for the 19 mm ? 19 mm csp_bga package in figure 65 are shown in millimeters. surface-mount design table 70 is provided as an aid to pcb design. for industry-stan- dard design recommendations, refer to ipc-7351, generic requirements for surface-mount design and land pattern standard . figure 65. 349-ball chip scale package ball grid array [csp_bga] (bc-349-1) dimensions shown in millimeters compliant to jedec standards mo-275-ppab-2. 1.10 ref a b c d e f g h j k l m n p r t v w aa ab u y 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 16 17 18 19 20 21 22 16.80 bsc sq 0.50 0.45 0.40 19.10 19.00 sq 18.90 coplanarity 0.20 bottom view detail a top view 1.50 1.36 1.21 0.35 nom 0.30 min ball diameter seating plane a1 ball corner a1 ball corner detail a 0.80 bsc 1.11 1.01 0.91 table 70. bga data for use with surface-mount design package package ? ball attach type package ? solder mask opening package ? ball pad size bc-349-1 solder mask defined 0.4 mm diameter 0.5 mm diameter
rev. 0 | page 109 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 automotive products some models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. note that these automotive models may have spec- ifications that differ from the commercial models and designers should review the product specif ications section of this data sheet carefully. contact your lo cal adi account representative for specific product ordering in formation and to obtain the spe- cific automotive reliability reports for these models. ordering guide model max. core clock temperature ? range 1 1 referenced temperature is ambient temperature. the ambie nt temperature is not a sp ecification. please see operating conditions on page 52 for the junction temperature (t j ) specification which is the only temperature specification. package description package ? option adsp-bf606kbcz-4 400 mhz 0c to +70c 349-ball csp_bga bc-349-1 adsp-bf606bbcz-4 400 mhz C40c to +85c 349-ball csp_bga bc-349-1 adsp-bf607kbcz-5 500 mhz 0c to +70c 349-ball csp_bga bc-349-1 adsp-bf607bbcz-5 500 mhz C40c to +85c 349-ball csp_bga bc-349-1 ADSP-BF608kbcz-5 500 mhz 0c to +70c 349-ball csp_bga bc-349-1 ADSP-BF608bbcz-5 500 mhz C40c to +85c 349-ball csp_bga bc-349-1 adsp-bf609kbcz-5 500 mhz 0c to +70c 349-ball csp_bga bc-349-1 adsp-bf609bbcz-5 500 mhz C40c to +85c 349-ball csp_bga bc-349-1
rev. 0 | page 110 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609
rev. 0 | page 111 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609
rev. 0 | page 112 of 112 | june 2013 ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. ? d10659-0-6/13(0) adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609

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